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 > Datasheets
ADM-XRC> Xilinx reconfigurable computer
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The ADM-XRC is a high
performance reconfigurable
PMC (PCI Mezzanine Card)
based on the Xilinx Virtex
and Virtex-E range of
FPGAs. The ADM-XRC complements
the Virtex with PCI interface,
external memory, high
density I/O, programmable
clocks and flash boot
facilities. A comprehensive
cross platform API with
support for WinNT/2000/XP,
linux and VxWorks provides
access to the full functionality
of these hardware features
and the Virtex-II devices.
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Industry standard Xilinx Virtex based PMC format
ideal for prototyping, integrating and embedding IP
cores
Adapters available for PCI, CompactPCI and VME
Support for the largest Xilinx Virtex devices from
XCV405E to XCV2000E
Flash memory for embedded configuration
High performance bus mastering PCI interface with
twin DMA
High density I/O connector in standard SCSI-2 format
or optional rear panel I/O via Pn4
Support for Xilinx ChipScope
4 independent banks of 256K(512K) x 36 bit ZBT SRAM
Programmable clock generator
Drivers for WinNT, Win2K, WinXP, VxWorks and Linux
Common API for easy cross platform development
Example apps include DMA, ZBT access and FFT in Verilog
and VHDL
| Feature |
Specification |
| FPGA |
Xilinx Virtex V400-V1000
Xilinx Virtex-E V1000E-V2000E
Xilinx Virtex-EM V405E-V812E
All BGA 560 devices
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| PCI
Bus |
Universal PCI rev 2.2 compliant
PLX 9080 ASIC with 33MHz 32-bit PCI bus and
33MHz 32-bit local bus. Twin DMA controllers,
fifo and interrupt controller peak data rate
132MBytes/sec
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| SRAM |
4 independent banks ZBT SSRAM 256K (512K) x
36
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| Front I/O |
SCSI style 68-way
connector with 34 I/O connections to Virtex |
Rear I/O |
Optional 53 I/O
connections via PMC Pn4 connector |
| Clocks |
On board clock
generator provides a synchronous local bus clock
for
the PCI interface and the Virtex FPGA.
A second clock is provided to the Virtex FPGA
for user applications and can be free running
or stepped under software control.
Both clocks are programmable and can be used by
the Virtex Clock
DLL functions:-
Local Bus
400kHz to 40 MHz
User Clock
0Hz to 100MHz |
| Configuration |
PCI Bus direct
to SelectMAP port
From Flash direct on power up
External JTAG connector |
| SelectMap |
Configuration
port supports direct access to Virtex-II configuration
for download or readback. DMA can be used for
rapid configuration. Support for Xilinx ChipScope®. |
| Ordering Information
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ADM-XRC/xxxx-y(/z)
xxxx - Virtex device
y - Virtex speed 4 / 5 / 6 / 7 / 8
z - ZBT memory size 4=4MBytes 8=8MBytes
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(C) Copyright 2006 Alpha Data. All Rights Reserved
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