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ADP-WRC-II> Wide Memory Xilinx Virtex-II PCI card
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The ADP-WRC-II is a high performance
reconfigurable PCI card based on the
Xilinx Virtex-II range of Platform
FPGAs. Features include two banks
of very high bandwidth memory, 64/66
PCI interface, CMC daughter board
interface, programmable clocks, battery
backed encryption and flash boot facilities.
A comprehensive cross platform API
with support for WinNT/2000/XP, Linux
and VxWorks provides access to the
full functionality of these hardware
features.
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| Feature |
Specification |
| FPGA |
Xilinx Virtex-II
2V6000, 2V8000
Supports all speed grades
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| PCI
Bus |
Universal PCI rev 2.2 compliant
PLX 9656 ASIC with 66MHz 64-bit PCI bus
and 66MHz 32-bit local bus. Twin DMA controllers,
fifo and interrupt controller peak data
rate 528MBytes/sec
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| Memory |
DDR SDRAM
1 GByte - 2 independent banks 16M x 256
2 GByte - 2 independent banks 32M x 256
(optional)
peak memory bandwidth 12.8 GByte/sec
Flash
16MBytes
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I/O |
Via CMC (Common Mezzanine Card)
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| Clocks |
On board clock generator provides
a synchronous local bus clock for the PCI
interface and the Virtex FPGA.
A second clock is provided to the Virtex FPGA
for user applications and can be free running
or stepped under software control.
Both clocks are programmable and can be used
by the Virtex Clock
DLL functions:-
Local Bus
400kHz to 66 MHz
User Clock
0Hz to 100MHz |
| Configuration |
PCI Bus direct to SelectMAP
port
From Flash direct on power up
External JTAG connector |
| SelectMap |
Configuration port supports
direct access to Virtex-II configuration for
download or readback. DMA can be used for
rapid configuration. Support for Xilinx ChipScope®. |
| Encrypting |
Dual battery back-up for Virtex-II
encryption keys |
| Software
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Drivers for WinNT, 2000, XP,
linux and VxWorks
API with template designs in VHDL and Verilog |
| Ordering
Information |
ADP-WRC-II/xxxx-y/m
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| parameter |
description |
options |
xxxx
y - 4, 5, 6
m
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Virtex device
Virtex speed
GByte DDR SDRAM
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6000, 8000
4, 5, 6
1 (std), 2
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(C) Copyright 2006 Alpha Data. All Rights Reserved
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