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Reference Design - RD-7V3

V1.0 : 10th June 2015


The RD-7V3 provides a fully functional PCI Express Bridge interface with direct slave and DMA engine driven user interfaces, memory management interface and initial external IO interfaces for 10G Ethernet and SATA.

The reference design includes:

    -    Example "getting started" projects for Vivado IP Integrator.

    -    PCIe Backend IP core encrypted netlist, including high-performance scatter-gather DMA engines

    -    Board management and monitoring VHDL source code

    -    Comprehensive host device drivers for Linux and Windows 7

    -    Linux and Windows 7-64 bit edition API

    -    Bit-file reference design for SODIMM

    -    Reference design to demonstrate 10G Ethernet PHY connectivity

Also included is access to the Alpha Data Support download lounge for latest updates.

Note: RD-7V3 is not required if the intended for Xilinx SDAccel development.

Design Flow

Classic Hardware Design Flow

Reference designs available:

Example DesignDescriptionComes with RD-7V3
Getting Started Block Diagrams
Basic PCIe Block Diagram DemoSimple PCI Express End Point with memory mapped interface
SDRAM PCIe Block Diagram DemoSimple PCI Express End Point attached to onboard memory
SFP+/QSFP+ IBERT Loopback DemoBasic 10G/25G loopback test for SFP+/QSFP using pseudo random tester
SFP+/QSFP 10GE XGMII Loopback Demo10G XGMII to SFP+/QSFP tester
SATA MAC IP and example PHYLow Level SATA controller design
DMA Streaming Block Diagram DemoExample system using DMA across PCI Express to transfer data
dimm_testMemory Interface example Design-
reg_accessPCIe Register Access Example-
dma_demoPCIe DMA Performance Example-


- Available

- In Development



Related Board


photo of ADM-PCIE-7V3Block diagram of ADM-PCIE-7V3


Product Support

Alpha Data also provide initial email and telephone support for these products. Long term support can also be purchased as well as design services.

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