Alpha Data PCI Express Gen3 Reference Design Kit - Beta Release
Reference Design Kit - An Overview
The PCIE Gen3 Reference design has been designed to be installed on the Xilinx VC709 demonstration board. The design is provided with a demo core which runs for a limited time only after reset. A VC709 board locked core is available for prospective Alpha-Data customers on request. Alpha-Data customers who purchase an ADM-XRC-7V1 or ADM-VPX3-7V2 will be entitled to an unlocked core.
The purpose of this reference design is to provide an easy migration path from the Xilinx VC709 low cost demonstration board which many customers may choose for their initial Reference to a deployable solution, suitable for rugged environments, such as the ADM-XRC-7V1 or ADM-VPX3-7V2. The provision of the Alpha Data PCIe Gen3 backend IP, allows the use of the Alpha Data ADB3 driver and ADMXRC3 SDK to be used in the host software Reference. The backend IP provides direct memory mapped bus access from the processor's memory map into the FPGA. It also provides 4 high performance, 64-bit addressing capable, scatter gather DMA engines, each with their own independent memory mapped bus into the FPGA.
The reference design contains the following:
- VHDL top level design files
- an .NGC core containing the PCIe core and backend
- Makefiles for ISE 14.6 and/or Vivado 2013.2 or later.
- Makefiles can optionally use either Vivado 2013.2 or ISE 14.6 for implementation and bitstream generation.
- Source code and Windows executables for applications which measure the DMA performance, and test a wide range of possible DMA transfers. To compile these designs for Linux or VxWorks you will need to install the SDK.
The reference design is compatible with the Alpha Data ADB3 driver for Virtex 6 and Virtex 7 boards. This driver is available for Windows, Linux and vxWorks, and will need to be installed to run any host applications. The reference design is compatible with several of the standard ADMXRC3 SDK applications, such as dump and info.
The backend interface to the user is provided as 5 OCP-IP memory mapped ports (128 bit wide for Direct Slave, and 256 bit wide for DMA transfers). These are similar to, but not identical to AXI-4 interfaces (full memory mapped, burst capable), and simple conversion blocks with minimal logic are available.
The PCI Express Gen 3 Reference Design Kit can be downloaded from the Alpha Data FTP site: PCI Express Gen3 Reference Design Kit.
Contact Sales at Alpha Data for further information.
 : Subject to minimal firmware modification. Contact Alpha Data for further details.