XRM-ADC-Q8 related documents

Datasheet (0.38MB)

XRM-ADC-Q8




Photo 1 of xrm-adc-q8Photo 2 of xrm-adc-q8Main Photo of xrm-adc-q8 I/O Module: XRM-ADC-Q8 : Quad Analog to Digital Convertors 14-bit at 250MHz sampling rate. Includes ext clock and trigger inputs

Features

  • Quad ADC Input
  • Clock In
  • Auxiliary I/O port
  • The XRM has built-in thermal monitoring of the ADC
  • Example UCF, HDL files and Application software are provided with the board.

Applications

  • IF/Baseband Signal Sampling

Summary

The XRM-ADC-Q8 is an I/O Module which provides four Analog to Digital convertors with 14-bit resolution at sampling rates up to 250MHz.

The XRM is aimed at IF/Baseband Signal Sampling. An external clock source may be used or an internally generated clock can be used to provide the sampling clock. An Auxiliary I/O port is provided for use as a trigger input and general purpose signaling. An additional two ports are available for use as high-speed interconnect between boards for synchronisation.. The built-in thermal monitor allows the user to check the operating temperature of the ADC. Provided as part of the sample design is the functionality to read the temperature of the device, and software to monitor this and recalibrate the ADC if the thermal drift is sufficient. The software will also shut the ADC down if the device starts to go over the maximum operating temperature.

Note: To ensure XRMs and XRM2s cannot be inadvertently installed on non-compatible FPGA platform boards the XRM2 connectors are mounted rotated 180° from those on XRM IO Modules. Most photographs of our mature XRM IO Modules are of the XRM version.




XRM-ADC-Q8 Detailed Specification

Product

XRM-ADC-Q8

Type

XRM

Functional Summary

The XRM-ADC-Q8 is an I/O Module which provides four Analog to Digital convertors with 14-bit resolution at sampling rates up to 250MHz.

Functional Description

The XRM is aimed at IF/Baseband Signal Sampling. An external clock source may be used or an internally generated clock can be used to provide the sampling clock. An Auxiliary I/O port is provided for use as a trigger input and general purpose signaling. An additional two ports are available for use as high-speed interconnect between boards for synchronisation.. The built-in thermal monitor allows the user to check the operating temperature of the ADC. Provided as part of the sample design is the functionality to read the temperature of the device, and software to monitor this and recalibrate the ADC if the thermal drift is sufficient. The software will also shut the ADC down if the device starts to go over the maximum operating temperature.

Software

Example UCF, HDL files and Application software are provided with the board.

Applications

IF/Baseband Signal Sampling

XRM I/O

Signal Input
Channels:

4

fmax:

250Msps

type:

ADC

Resolution:

14-Bit

BandWidth:

4.5MHz to 700MHz

levels:

+10dBm

Impedance:

50 Ohm

Connector:

SSMC

Information:

Note: exceeding the maximum signal limit may result in permanent degradation of converter performance.

Clock In
Channels:

1

type:

Clock

fclock:

Fmax

levels:

3v3

Impedance:

Impedance?

Information:

Note: Exceeding the maximum voltage limit may result in permanent degradation of converter

Aux IO Port
Channels:

2

type:

I/O

levels:

2V5 Logic (dc coupled)

Connector:

UFL

Information:

User configurable as inputs or outputs, signals direct to FPGA pins.

Note: signals on these connectors must be restricted to 2V5 logic otherwise damage may result.

Environmental Specification

TEMPERATURE :

Air cooled option

Operating Temperature 0° to +55°C†

Non-Operating(Storage) Temperature -40° to +85°C

Operating Humidity 5% to 95% at 40°C non-condensing

Non-Operating(Storage) Humidity 5% to 95% at 40°C non-condensing

† - It is essential that sufficient air-cooling is provided, if thermal monitoring is provided on board then this should be used to shut the device down if it starts to overheat in order to reduce the possibilty of damaging the devices.


EMC :

FCC 47CFR Part 2

EN55022 Equipment Class B


For more information on the operating conditions for the different cooling options go to:
Alpha Data Environmental Specification Page.

Or read:
the Alpha Data Environment Specification (PDF).

XRM-ADC-Q8 Order Code Information

Product code

XRM(xver)-ADC-Q8(io)(h)

XRM Version

xver

blank=Original XRM (FPGA products up to Virtex-5),

2=XRM Version 2 (FPGA products Virtex-6 and later)

Voltage Option

io

blank = LVTTL I/O levels,

/5V = TTL I/O Levels

Heatsink

h

blank = No Heastink,

/HTSK-XRM-ADC-HS-1 = Heatsink Fitted


Sample Code :

XRM-ADC-Q8


Order Code generation for the XRM-ADC-Q8

Go to Order Code Generation Page which allows the generation of specific order codes. The numbers created on this page are for illustration purposes, please contact Alpha Data for more information.


Sales Questions

For any sales questions regarding the XRM-ADC-Q8, please e-mail us at:

sales@alpha-data.com


Technical Support

For any technical questions regarding Alpha-Data products please e-mail us at:

support@alpha-data.com




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