Each FPGA board contains a parallel Flash connected to the bridge FPGA. Upon initialisation of the bridge it examines the Flash contents and if a target design has been stored in it the bridge will configure the target FPGA with this BIT file.

In the SDK bin directory is a program called flash.exe, run this in the command line with the syntax:

flash.exe program target.bit

where target.bit is the name of your bit file.

All XRMs, which have this facility, use SR60 or equivalent batteries.

This varies greatly depending on the target FPGA device that is selected and the resources consumed by the user design. As a general rule of thumb, the Alpha-Data PMC boards with smaller Virtex5 devices (SX95T,LX110T) require 4-5 Watts of power in the idle state. The user design can add an additional 5-15 Watts of power depending on the size of the user design. Alpha-Data provides estimation tools with our products which can be used in conjunction with the Xilinx^® XPE tool

All of the Alpha-Data Virtex-4 and Virtex-5 PMC boards can be used in a PCI-Express system via a PCI-Express carrier. Alpha-Data offers the ADC-EMC for a dual PMC solution in a PCI-Express environment. Half length single PMC carriers are also widely available from 3rd party vendors.

The entire target device is available for the user design. When host access to the FPGA is required, the host interface (via local bus) typically consumes less than 1% of the target FPGA resources

There are 3 different methods that can be used for maximum flexibility.

1) Via the JTAG chain using a Xilinx^® Platform Cable. This is to program the FPGA directly. DO NOT program the FLASH device in the JTAG chain as this is this device is for the bridge ONLY.

2) Directly from the host computer. The Alpha-Data API provides functions to do this using the example designs and user applications.

3) Via the onboard flash memory. An API function is also provided to access the flash on the board, and the 'flash' example application provides a means to program and verify the flash device.

Yes, there is a comprehensive Software Development Kit (SDK) provided with our hardware. This contains a number of executables to access and test the various features of the hardware. The source code, FPGA designs, and documentation are also provided in the SDK. In addition, many of our XRM modules are provided with application specific example designs. These provide a working turn-key system that can easily be customized.

The current FPGA technology allows for a great deal of flexibility I/O standards. Alpha-Data hardware is designed to use the entire spectrum of Select IO technology, and maintain signal integrity. For specific interfaces, refer to the relevant FPGA device datasheet.

Alpha-Data can customize our products for your requirements. Many of the products can be readily customized with different memory sizes, clock frequencies, I/O Terminations, and settings. Contact us with your specific needs.

A new application will require the following tools: Xilinx^® ISE, a C compileer for your operating system, and the Alpha-Data SDK.

The Xilinx^® ISE WebPACK can be dowloaded free from the Xilinx^® website.

the Microsoft Visual C++ Express Edition can be downloaded free .

The Alpha-Data SDK is provided as part of the purchase price with our hardware.

Also recommended for fast development and debugging of new designs are: ModelSim Simulator and Xilinx^® Chipscope.

All goods from Alpha-Data carry a 6 months free support service. This service is available by letter, phone, fax, and email. Technical support contracts for longer periods are available upon request. Support contracts for software components also normally cover the cost of updates/upgrades.

All Alpha-Data products enjoy parts and labor warranty for 12 months after purchase. The warranty is based on the customer returning the defective goods to Alpha-Data for repair or replacement, which will be at the discretion of the company. The warranty does not cover damages caused by negligence, misuse, and normal wear and tear. No liability is accepted by the company for any damage caused by the use of its hardware or software.

Alpha-Data is comitted to environmental protection, and the the majority of our products are produced as RoHS 6 of 6 compliant. We will continue to use lead-free processes when ever possible. Please contact Alpha-Data for specific product lead-free status.

Yes, Alpha-Data can provide a custom XRM module to suit specific requirements. The necessary information can also be provided to the customer to produce their own XRM designs.

The XMC is the same format as the PMC except it has extra connectors to the carrier allowing direct high-speed serial communication to the system. This can be PCI-Express or Serial Rapid IO. The newer Alpha Data PMC products have an option to have the High Speed I/O (equivalent of J15 on an XMC) board) connector fitted (/X on the order code). The high-speed serial lanes connect to the Target FPGA allowing the user application to incorporate the link directly into their design. Note, however, that this does not make the board an XMC product - it still requires the PMC connectors for the provision of power to the board.

The more recent products have been designed to allow the fitting of a heatsink and/or bolting to the carrier cooling system. See Ruggedised versions of Alpha Data Products.

The option is available for a selection of Alpha Data products. Contact Alpha Data for more information. See Ruggedised versions of Alpha Data Products.

The basic version of Alpha Data boards. This indicates that the board requires only convection cooling. The boards may still heat up if there is insufficient air flow to allow convection cooling to work optimally. See Ruggedised versions of Alpha Data Products.

The convection cooled industrial version of Alpha Data boards. This indicates that the board requires only convection cooling, it uses industrial grade components and may have a heatsink fitted. The boards may still heat up if there is insufficient air flow to allow convection cooling to work optimally. See Ruggedised versions of Alpha Data Products.

The conduction cooled version of Alpha Data boards. This indicates that the board has been designed to bolt onto the carriers cooling system. The board shall also be fitted with industrial grade components. See Ruggedised versions of Alpha Data Products.

Some of Alpha Data's boards are designed to allow heatsinks to be fitted to them. Contact Alpha Data for more information. See Ruggedised versions of Alpha Data Products.

use the command line 'bitdir' switch. The app is invoked using a command similar to

xrc-5t-da1.exe /bitdir MyFolder\MySubFolder

where 'MyFolder\MySubFolder' is the path to the 'xrc-5t-da1' folder that contains the bit file.

Yes, older product datasheets are viewable from the websites older product page. ADM-A2D, ADM-XP, ADM-XPL, ADM-XRC, ADM-XRC-II LITE, ADM-XRC-II, ADP-DRC-II, ADP-WRC-II, ADP-XPI.

It is possible to set the startup MCLKA and MCLKB frequencies by setting the word with index 0x101 in nonvolatile memory for Vital Product Data. This method of programming will only change the clock frequency at power up; the change doesn't take effect until then. The 32-bit MCLK word at VPD location 0x101 has several fields, which are as described in the ICS834034-01 data sheet:

8:0 = M multiplier value

11:9 = NA divide select; 0 => /1, 1 => /2, 2 => /3, 3 => /4, 4 => /5, 5 => /6, 6 => /8, 7 => /16

14:12 = NB divide select; 0 => /1, 1 => /2, 2 => /3, 3 => /4, 4 => /5, 5 => /6, 6 => /8, 7 => /16

16:15 = always 0

29:17 = always 0

30 = reference oscillator select; 0 => 25 MHz, 1 => 26.5625 MHz

31 = always 0

The formula for MCLKA frequency is f = f_ref * M / NA_divide.

The formula for MCLKB frequency is f = f_ref * M / NB_divide.

There is also a PLL constraint that 490 <= f_ref * M <= 640, which places limits on the M values depending on which reference oscillator is selected.

So the value 0x40001416 corresponds to

M = 22

NA = 2 => NA_divide = 3

NB = 1 => NB_divide = 2

Oscillator select = 1 (26.5625 MHz)

PLL Frequency = 584.375 MHz (within limits of 490 - 640 MHz)

MCLKA = 194.7916 MHz

MCLKB = 292.1875 MHz

If you want to clear that value for some reason, so that MCLK doesn't get programmed and is left at the hardware default, you should write 0xFFFFFFFF, e.g.

eptest 0x101 0xFFFFFFFF

Also, if you inadvertently put a incorrect value in and the board stops working, you can recover by fitting a jumper link across pins 2 and 3 of J5 . This disables both setting MCLK and configuring the FPGA from Flash so that you will be able write 0xFFFFFFFF.

To verify that the clock setting is loaded correctly at power-up, run the 'clock' application to get an approximate cycle count of the clock over 1 second:

clock 2 (MCLKA)

clock 3 (MCLKB)

It is possible to set the startup LCLK frequency by setting the word with index 0x100 in nonvolatile memory for Vital Product Data. This method of programming will only change the clock frequency at power up; the change doesn't take effect until then.

1. Using the desired LCLK frequency, calculate a multiplier and divider pair using the following equation: lclk frequency = 200 * M / D (in MHz)

NOTE: The lowest possible M & D values should be used as higher values generally result in more jitter.

NOTE: lclk frequency should not exceed 80 MHz!

2. Given M and D, generate a 32-bit value as follows:

val32(15:0) = M-1

val32(31:16) = D-1

where 2 <= M <= 32, 1 <= D <= 32

3. Then program the value into the VPD memory using the following command:

eptest 0x100 (val32)

NOTE: it is important to write (val32) as a hex number prefixed by 0x.

Example: to program LCLK for 57.14 MHz, D = 7 and M= 2

eptest 0x100 0x00060001

If you want to clear that value for some reason, so that LCLK doesn't get programmed and is left at the hardware default, you should write 0xFFFFFFFF, e.g.

eptest 0x100 0xFFFFFFFF

Also, if you inadvertently put a incorrect value in and the board stops working, you can recover by fitting a jumper link across pins 2 and 3 of J5 . This disables both setting LCLK and configuring the FPGA from Flash so that you will be able write 0xFFFFFFFF.

To verify that the clock setting is loaded correctly at power-up, run the 'clock' application to get an approximate cycle count of the clock over 1 second:

clock 1

The signals to P6 differ from those to P4:

The GPIO signals to/from P6 go through auto-sensing level translators (TXB0108) with 3.3V at the XMC connector, and 1.5V at the FPGA.

The signals should all have IOSTANDARD = LVCMOS_15 at the FPGA.

The signals are all routed single-ended and the level translator adds some delay and skew. Therefore, I recommend these lines are only used for low-frequency signalling.

The buffer delays are:

Outputs (FPGA -> P6) min=1.1ns, max=10ns.

Inputs (P6 -> FPGA) min=0.4ns, max=11.7ns.

Max channel-channel skew in either direction is 1.6ns

TI TXB0108 Product page

The GPIO signals to/from P4 go through a FET bus switch (Pericom PI5C34X245).

The 2.5V outputs from the FPGA pass straight through the bus switch to P6. These outputs will be compatible with 2.5V or 3.3V input levels.

Inputs at P6 are 3.3V compatible with levels above 2.5V clamped by the bus switch.

The signals are all routed as differential pairs, allowing use as single-ended (LVCMOS_25) or differential (LVDS_25).

The bus switch adds no propagation delay and the signals on P4 are suitable for high-frequency operation. The Xilinx^® App Note #860 shows an excellent method of running high-speed LVDS intefaces.

Xilinx^® App Note 860

There are two SDK packages available:
Gen 2 - This is for use with the Virtex-2, Virtex-4 and Virtex-5 based FPGA boards. All these products use the PCI interface protocol.
Gen 3 - This SDK is for use on the Virtex-6 family of FPGA boards. All these products use the PCI-Express interface protocol.

When generating the bitfile for the Target FPGA of your board use the following options (either through the GUI or on the command line):

-g UnusedPin:Pullnone : this disables pull up/down on unused pins
-g DriveDone:yes : ensures the Target FPGA drives done at the end of programming
-g Compress : creates a compressed bit file, reduces bitfile size and so reduces configuration time for the Target FPGA.

See Xilinx^® User Guide UG628 for full details of options.