Alpha Data Release version 3.1 of the Camera Interface Development Kit - CL3

July 2017: Edinburgh, UK

With the high resolution and frame rates of modern video cameras it has become essential that the raw video stream is processed in hardware prior to being transferred to software for final image processing. To facilitate this Alpha Data continues to develop both hardware interfaces for various camera protocols and extend the software development Kit (CL3) to handle the heavy lifting requirements such as frame capture and store, region of interest windowing and frame transfer to the host system.

CL3 Data Flow Block Diagram

Camera Interface Modules Supported by CL3

  • Camera Link - Base
  • Camera Link - Full
  • Camera Link - Dual
  • CoaXPress - (Basic example provide, most support available on request)
  • DVI-D - (Available on request)

The CL3 Development Kit Overview

Hardware Layer

This layer provides connectivity between imaging devices, the Target FPGA and the host system. The Target FPGA can be used by developers to perform their desired image processing task. In addition to the Target, most Alpha Data re-configurable co-processors devices have a Bridge chip. This provides a connection to the Host system running the Software Layer. On Alpha Data devices without Bridge chips a Bridge core (normally PCIe) can be directly included in the Target FPGA. Implementation details of this are Alpha Data device specific.

The Hardware Layer of the SDK should be used for as much computational intense processing of the input image stream(s) as possible. In the developer's application it may be the case that acquisition of images by the Host is not necessary. However, for debugging, it is recommend that the developer keeps this capability provided by the example designs (before any processing is performed) so that verification of acquisition of the raw image can be performed.

Software Layer

The lowest level of interaction between the Hardware and Software Layers take place via a device driver, for example Alpha Data's ADB3 driver. The driver provides the means to monitor interrupts, access the target FPGA as a Direct Slave, and initiate DMA's between the Target FPGA's attached memory and the Host memory.

Above the driver level the CL3 SDK provides a C++ software API. This provides classes that can be used to interact with the Hardware Layer (via the driver). The CL3 API classes include the following functions:

Further information can be found on the CL3 Webpage

About Alpha Data

Established in 1993, Alpha Data is a world leader in high performance Xilinx FPGA based plug-in acceleration boards for Data Center and high-performance computing applications including video processing, machine learning, and network acceleration. Alpha Data’s low-cost, power-efficient accelerators leverage Xilinx’s All Programmable FPGAs and the SDAccel development environment for Open CL, C and C++ to accelerate processing, increase data throughput, and deliver power optimized solutions for computing clusters. Designed to be server-friendly for large scale data center deployment, Alpha Data’s range of FPGA accelerator boards are all in a low-profile PCIe format with passive cooling.
For more information on Alpha Data and its products, please visit www.alpha-data.com







©2017 Alpha Data Parallel Systems - All rights reserved