![]() | Product Features
Applications
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Product Summary The ADM-XRC-6T1 is a high performance reconfigurable XMC (VITA 42.3 Mezzanine Card) based on the Xilinx® Virtex-6 LXT and SXT ranges of Platform FPGAs. Features include PCI Express® Gen2 interface, external memory, high density I/O, temperature monitoring, battery backed encryption and flash boot facilities. A comprehensive cross platform API with support for Microsoft Windows™, Linux and VxWorks™ provides access to the full functionality of these hardware features. The optional fitting of the Pn4 connector provides an additional 64 General Purpose IO (GPIO) links to the carrier card. | |


XRM Connectors providing 146 discrete I/O and 8 High Speed Serial Links
Typical XRM is the XRM-DAC-D4/1G

Provides the user access to configure the Target FPGA and to run Chipscope on the active design

Allows host to configure system clocks, reload the target flash and directly program the target FPGA.
A back up battery can be used to give power to hold onto encryption keys if the design has been encrypted for security reasons.
Configuration Flash providing an initialisation design for automatic loading into the target FPGA.

Alpha Data proprietary firmware is provided for the bridge. It is automatically loaded into the bridge FPGA at power-up.
Provides PCI Express bus access to/from the host system. Includes multiple DMA engines for fast data transfer.
Uses a high speed duplex iinterface to the Target FPGA to maximise usable bandwidth from PCI Express.
PCI Express interface up to Gen2 x4 capable bridge FPGA.

Multiple DMA engines allowing fast data transfers to/from the FPGA.
DMA engines capable of being configured from the HOST system or the User application in the target FPGA.

Application/Target FPGA.
family : V6
footprint : FFG1759
devices : LX240T, LX365T, LX550T, SX315T, SX475T

1GByte in 4 independent banks (2GByte option) of DDR3 SDRAM @ 800MT/s (32-bit wide - 3.2GB/s)
The 6T1 has multiple High Speed Serial Link options through the XMC connectors P15 and P16.
4 lanes from P15 go to the PCI Express Bridge FPGA.
The other 4 lanes from P15 can be fed to the Target FPGA (2 always and 2 via an onboard HS Serial Switch selecting the 22 lanes from either P15 or P16).
Switches reside on back of board.
8 lanes connect from P16 directly to the Target FPGA along with 38 single ended digital I/O.
If P14 is fitted then an extra 64 General Purpose I/O signals are available.


The MPTL carries all the data traffic to and from the PCI Express Bridge to the Target Application. It consists of a 4 lane High-Speed Serial Link running at up to 5Gbits/s.
The MPTL passes direct transfer requests from the Host, DMA data transfers and low speed signal transfers.
| Product | ADM-XRC-6T1 | ||
| Board Format | XMC | ||
| Type | FPGA Board | ||
| Host Interface | PCI Express® Gen2 x4 | ||
| Functional Summary | The ADM-XRC-6T1 is a high performance reconfigurable XMC (VITA 42.3 Mezzanine Card) based on the Xilinx® Virtex-6 LXT and SXT ranges of Platform FPGAs. | ||
| Functional Description | Features include PCI Express® Gen2 interface, external memory, high density I/O, temperature monitoring, battery backed encryption and flash boot facilities. A comprehensive cross platform API with support for Microsoft Windows™, Linux and VxWorks™ provides access to the full functionality of these hardware features. The optional fitting of the Pn4 connector provides an additional 64 General Purpose IO (GPIO) links to the carrier card. | ||
| Target Device(s) | family : V6 footprint : FFG1759 devices : LX240T, LX365T, LX550T, SX315T, SX475T | ||
| Host Interface | PCI Express® Gen2 x1, x2 or x4 link to separate bridge device with 2GB/s local link to user FPGA 4 DMA Controllers Interrupt Controller | ||
| On board memory | SDRAM : 1GByte in 4 independent banks (2GByte option) of DDR3 SDRAM @ 800MT/s (32-bit wide - 3.2GB/s) FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA. | ||
| Software | Drivers for Microsoft Windows™, Linux and VxWorks™ API with template designs in VHDL | ||
| Applications | Radar/Sonar Beamforming ELINT Fingerprint Recognition Data Encryption | ||
| Front Connector I/O |
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| Rear Connector IO |
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| Board Configuration | Clocks : Low-jitter 250MHz reference clock, suitable for SerDes applications Low-jitter 200MHz reference clock for IOB delay circuits Custom clock inputs available through the XRM interface FPGA : PCI Express® direct to SelectMAP port From Flash direct on power up External JTAG connector | ||
| Battery | Battery back-up for IP encryption keys | ||
| Cooling Options | Air Cooled Commercial (standard) AC1 - air cooled industrial CC1 - conduction cooled industrial | ||
| Environmental Specification | Temperature : Air cooled option Operating Temperature 0° to +55°C Non-Operating(Storage) Temperature -40° to +85°C Operating Humidity 5% to 95% at 40°C non-condensing Non-Operating(Storage) Humidity 5% to 95% at 40°C non-condensing EMC : FCC 47CFR Part 2 EN55022 Equipment Class B | ||
Further Environmental Information can be found by reading: |
| Product code |
ADM-XRC-6T1/z-y(m)(c)(p) | |
Virtex-6 device | z | LX240T, LX365T, LX550T, SX315T, SX475T |
Virtex-6 speed | y | 1, 2, 3 |
Memory Size Fitted | m | blank = 1GByte, /2 = 2GByte |
Cooling | c | blank = air cooled commercial, /AC1 = air cooled industrial, /CC1 = conduction cooled industrial |
Pn4 Fitted | p | blank = not fitted, /Pn4 = Pn4 Connector fitted |
Note | not all FPGA speed grades available in all configurations. Contact Alpha Data for full details. | |
Order Code Rules: When Conduction Cooled selected -3 devices are not available When Air Cooled Industrial selected -3 devices are not available When LX550T selected, -3 devices are not available When SX475T selected, -3 devices are not available | ||
Sample Code :
ADM-XRC-6T1/LX240T-1
Go to Order Code Generation Page which allows the generation of specific order codes. The numbers created on this page are for illustration purposes, please contact Alpha Data for more information.
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