Alpha Data Product : ADM-XRC-6TGE

ADM-XRC-6TGE Overview Block Diagram Specification Ordering Info

Product Features

Board Format : XMC
Host I/F : PCI Express^® Gen2 x4
Target Device(s) : Xilinx Virtex-6 {LX240T, LX365T, LX550T, SX315T, SX475T} (FFG1759)
SDRAM : 1GByte in 4 independent banks (2GByte option) of DDR3 SDRAM @ 800MT/s (32-bit wide so 3.2GB/s)
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Drivers for Microsoft Windows™, Linux and VxWorks™
The ADM-XRC Gen3 SDK provides the example C and HDL source code, giving software engineers and FPGA designers a head start in creating applications.

Applications

Radar/Sonar Beamforming
ELINT
Image/Video Processing
Data Encryption

Product Summary

The ADM-XRC-6TGE is a high performance reconfigurable XMC (VITA 42.3 Mezzanine Card) based on the Xilinx^® Virtex-6 LXT and SXT ranges of Platform FPGAs.

Features include PCI Express^® Gen2 interface, external memory, high density I/O, temperature monitoring, battery backed encryption and flash boot facilities.

A 10/100/1000Base-T Ethernet interface to the target FPGA is provided through the rear Pn6 connector.

A comprehensive cross platform API with support for Microsoft Windows™, Linux and VxWorks™ provides access to the full functionality of these hardware features.

The optional fitting of the Pn4 connector provides an additional 64 General Purpose IO (GPIO) links to the carrier card.

Product

ADM-XRC-6TGE

Board Format

XMC

Type

FPGA Board

Host Interface

PCI Express^® Gen2 x4

Functional Summary

The ADM-XRC-6TGE is a high performance reconfigurable XMC (VITA 42.3 Mezzanine Card) based on the Xilinx^® Virtex-6 LXT and SXT ranges of Platform FPGAs.

Functional Description

Features include PCI Express^® Gen2 interface, external memory, high density I/O, temperature monitoring, battery backed encryption and flash boot facilities.

A 10/100/1000Base-T Ethernet interface to the target FPGA is provided through the rear Pn6 connector.

A comprehensive cross platform API with support for Microsoft Windows™, Linux and VxWorks™ provides access to the full functionality of these hardware features.

The optional fitting of the Pn4 connector provides an additional 64 General Purpose IO (GPIO) links to the carrier card.

Target Device(s)

family : V6

footprint : FFG1759

devices : LX240T, LX365T, LX550T, SX315T, SX475T

Host Interface

PCI Express^® Gen2 x1, x2 or x4 link to separate bridge device with 2GB/s local link to user FPGA

4 DMA Controllers

Interrupt Controller

XRM Interface

The ADM-XRC-6TGE board implements the newer XRM2 interface.

IO Modules Compatible with ADM-XRC-6TGE

XRM-10G-QSFP, XRM-ADC-D2/125, XRM-ADC-D3/1G5, XRM-ADC-D6/250, XRM-ADC-D7-500, XRM-ADC-S4/3G, XRM-CLINK-MINI, XRM-CLINK-ADV, XRM-CLINK-H264, XRM-CLINK-GIGE, XRM-FCN, XRM-FCN-C1, XRM-FPDP, XRM-HSSDC2A, XRM-IO146, XRM-IO146-ROCKET, XRM-IO34, XRM-OPT, XRM-RIO, XRM-RS422, XRM-RS485, XRM-ZBT

Carriers Compatible with ADM-XRC-6TGE

ADC-PCIE-XMC, ADC-VPX3-XMC, ADC-XMC-II, ADC-EMC

On board memory

SDRAM :

1GByte in 4 independent banks (2GByte option) of DDR3 SDRAM @ 800MT/s (32-bit wide so 3.2GB/s)

FLASH :

Configuration Flash providing an initialisation design for automatic loading into the target FPGA.

Software

Drivers for Microsoft Windows™, Linux and VxWorks™

The ADM-XRC Gen3 SDK provides the example C and HDL source code, giving software engineers and FPGA designers a head start in creating applications.

Applications

Radar/Sonar Beamforming

ELINT

Image/Video Processing

Data Encryption

Front Connector I/O

Up to 146 LVCMOS/LVDS I/O

Programmable signaling levels of 1.5V, 1.8V or 2.5V

8 High-Speed Serial Links

Rear Connector IO

Pn5

x4 PCIe^® to Bridge FPGA or Target FPGA, x4 PCIe^® to Target FPGA, JTAG, I2C

Pn6

x4 MGT to Target FPGA, x4 MGT to Target FPGA or 10/100/1000Base-T to magnetics and Gigabit Ethernet PHY. (MAC to PHY Interface is SGMII), External MGT reference clock or 2 GPIO (Can be used single-ended or as 1 differential pair), 44 GPIO (Can be used single-ended or as 22 differential pairs)

Pn4

64 GPIO (Can be used single-ended or as 32 differential pairs)

Board Configuration

Clocks :

Low-jitter 200MHz reference clock

A programmable clock is available to the Target FPGA (configured by I²C)

Further custom clock inputs available through the XRM and Pn6 interfaces

FPGA :

PCI Express^® direct to SelectMAP port

From Flash direct on power up

External JTAG connector

Battery

Battery back-up for IP encryption keys

Environmental Specifications

Temperature Options:

AC0AC1CC1

Air Cooled Commercial (AC0)

Operating Temperature Range: 0°C to +55°C

Non-Operating (Storage) Temperature Range: -40°C to +85°C

Operating Humidity: up to 95% (non-condensing)

Heatsink: Finned low profile Black anodized aluminum

Air Cooled Industrial (AC1)

Operating Temperature Range: -40°C to +70°C

Non-Operating (Storage) Temperature Range: -55°C to +100°C

Operating Humidity: up to 95% (non-condensing)

Heatsink: Finned low profile Black anodized aluminum

Conduction Cooled Industrial (CC1)

Operating Temperature Range: -40°C to +70°C (85 with high efficiency system cooling - contact Alpha Data for more details)

Non-Operating (Storage) Temperature Range: -55°C to +100°C

Operating Humidity: up to 95% (non-condensing)

Heatsink: Flat face - 4 piece kit with Thermal pads to mate with most configurations of host metal work - (with or without: secondary ribs, standoff mountings) Black anodized aluminum

EMC:

FCC 47CFR Part 2

EN55022 Equipment Class B

Further Environmental Information can be found by reading:
The Alpha Data Environmental Specification

Product code	ADM-XRC-6TGE/z-y(m)(c)(p)(e)(g)
Virtex-6 device	z	LX240T, LX365T, LX550T, SX315T, SX475T
Virtex-6 speed	y	1, 2, 3
Memory Size Fitted	m	blank = 256MBytes per bank - 1GBytes for the board, /2 = 512MBytes per bank - 2GBytes for the board
Cooling	c	blank = air cooled commercial, /AC1 = air cooled industrial, /CC1 = conduction cooled industrial
Pn4 Fitted	p	blank = not fitted, /P = Pn4 Connector fitted
Replace Ethernet link on Pn6 with x4 MGT link	e	blank = 10/100/1000Base-T Ethernet link - x4 MGT on Pn6, /M = No Ethernet Link - x8 MGT link on Pn6
Replace Ref Clk 1 on Pn6 with 2 GPIO	g	blank = MGT clock input on Pn6 - 44 GPIO on Pn6, /G = no MGT clock input on Pn6 - 46GPIO on Pn6
Note		not all FPGA speed grades available in all configurations. Contact Alpha Data for full details.
Order Code Rules: -3 FPGA Speed option not available in Industrial parts for AC1 or CC1 When LX550T selected, -3 devices are not available When SX475T selected, -3 devices are not available

Sample Code :

ADM-XRC-6TGE/LX240T-1

Order Code generation

Go to Order Code Generation Page which allows the generation of specific order codes. The numbers created on this page are for illustration purposes, please contact Alpha Data for more information.