Alpha Data Product : ADPe-XRC-6TL

ADPe-XRC-6TL Overview Block Diagram Specification Ordering Info

Product Features

Board Format : PCI Express
Host I/F : PCI Express^® Gen2 x4
Target Device(s) : Xilinx Virtex-6 {LX130T, LX195T, LX240T, LX365T, SX315T, SX475T} (FFG1156)
SDRAM : 500MByte (option for 1GByte) in 2 independent banks of DDR3 SDRAM @ 800MT/s (32-bit wide so 3.2GB/s)
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Drivers for Microsoft Windows™, Linux and VxWorks™
The ADM-XRC Gen3 SDK provides the example C and HDL source code, giving software engineers and FPGA designers a head start in creating applications.

Applications

Radar/Sonar Beamforming
ELINT
Image/Video Processing
Data Encryption

Product Summary

The ADPe-XRC-6TL is a high performance reconfigurable PCI Express^® card based on the Xilinx^® Virtex-6 LXT and SXT ranges of Platform FPGAs.

Features include PCI Express^® Gen2 interface, external memory, High Pin Count (HPC) VITA 57 FMC I/O, temperature monitoring, battery backed encryption and flash boot facilities.

A comprehensive cross platform API with support for Microsoft Windows™, Linux and VxWorks™ provides access to the full functionality of these hardware features.

Product

ADPe-XRC-6TL

Board Format

PCI Express

Type

FPGA Board

Host Interface

PCI Express^® Gen2 x4

Functional Summary

The ADPe-XRC-6TL is a high performance reconfigurable PCI Express^® card based on the Xilinx^® Virtex-6 LXT and SXT ranges of Platform FPGAs.

Functional Description

Features include PCI Express^® Gen2 interface, external memory, High Pin Count (HPC) VITA 57 FMC I/O, temperature monitoring, battery backed encryption and flash boot facilities.

A comprehensive cross platform API with support for Microsoft Windows™, Linux and VxWorks™ provides access to the full functionality of these hardware features.

Target Device(s)

family : V6

footprint : FFG1156

devices : LX130T, LX195T, LX240T, LX365T, SX315T, SX475T

Host Interface

PCI Express^® Gen2 x1 (optionally x4) link to separate bridge device with 5Gb/s local link to user FPGA

2 DMA Controllers (4 in PCIe^® Gen2 x4 bridge option)

Interrupt Controller

On board memory

SDRAM :

500MByte (option for 1GByte) in 2 independent banks of DDR3 SDRAM @ 800MT/s (32-bit wide so 3.2GB/s)

FLASH :

Configuration Flash providing an initialisation design for automatic loading into the target FPGA.

Software

Drivers for Microsoft Windows™, Linux and VxWorks™

The ADM-XRC Gen3 SDK provides the example C and HDL source code, giving software engineers and FPGA designers a head start in creating applications.

Applications

Radar/Sonar Beamforming

ELINT

Image/Video Processing

Data Encryption

Front Connector I/O

High Pin Count (HPC) FMC Standard Connector

GPIO 80 pairs

GTX Links x10

Secondary Connector (KEL8831)

GPIO 64 signals

Rear Connector IO

No Rear I/O

Board Configuration

Clocks :

Low-jitter 250MHz reference clock, suitable for SerDes applications

Low-jitter 200MHz reference clock for IOB delay circuits

Custom clock inputs available through the FMC interface

FPGA :

PCI Express^® direct to SelectMAP port

From Flash direct on power up

External JTAG connector

Battery

Battery back-up for IP encryption keys

Environmental Specifications

Temperature Options:

AC0AC1

Air Cooled Commercial (AC0)

Operating Temperature Range: 0°C to +55°C

Non-Operating (Storage) Temperature Range: -40°C to +85°C

Operating Humidity: up to 95% (non-condensing)

Heatsink: Finned low profile Black anodized aluminum

Air Cooled Industrial (AC1)

Operating Temperature Range: -40°C to +70°C

Non-Operating (Storage) Temperature Range: -55°C to +100°C

Operating Humidity: up to 95% (non-condensing)

Heatsink: Finned low profile Black anodized aluminum

EMC:

FCC 47CFR Part 2

EN55022 Equipment Class B

Further Environmental Information can be found by reading:
The Alpha Data Environmental Specification

Product code	ADPe-XRC-6TL/z-y(m)(b)(c)
Virtex-6 device	z	LX130T, LX195T, LX240T, LX365T, SX315T, SX475T
Virtex-6 speed	y	1, 2, 3
Memory	m	blank=500MBytes, /1=1GBytes
Bridge Type speed	b	blank=PCIe^® Gen2 x1 with 2 DMA Engines, /B=PCIe^® Gen2 x4 with 4 DMA Engines
Cooling	c	blank = air cooled commercial, /AC1 = air cooled industrial
Note		not all FPGA speed grades available in all configurations. Contact Alpha Data for full details.

Sample Code :

ADPe-XRC-6TL/LX130T-1

Order Code generation

Go to Order Code Generation Page which allows the generation of specific order codes. The numbers created on this page are for illustration purposes, please contact Alpha Data for more information.