Resources for specific applications of our Data Center products.
Breaking Memory Bandwidth Barriers using High Bandwidth Memory FPGA (ad-an-0066)
The release of Virtex Ultrascale+ High Bandwidth Memory(HBM) FPGA devices, opens up whole new areas of memory bound applications to the benefit of power efficient FPGA acceleration. A recent increasing trend has been to target a variety of memory bound applications to GPU systems, simply because of their significant memory bandwidth advantage over the CPU, and this is despite the application not having any need for the GPUs primary functionality: the very high performance parallel floating point arithmetic. With the advent of FPGAs with similar external memory bandwidth, but much more flexible and higher internal memory bandwidth configurability, more customized and energy efficient accelerated solutions for these problems are now possible.
An Open Source FPGA CNN Library (ad-an-0055)
Convolutional neural networks have become the core component of a large number of hyperscale deployed machine learning algorithms used in image and vision recognition tasks. Low-bitwidth FPGA implementations of these networks provide a potential path to higher throughput and lower power machine learning inference solutions.
One purpose of this toolbox is to provide an easy path for developers to investigate the accuracy implications of switching from floating point defined network weights to low bitwidth fixed point weights on each of the layers making up the network.
Another purpose of this toolbox is to provide tools and knowledge for comparing network structure and size with on-chip memory and processing capabilities of FPGAs to aid in optimal device selection.
FPGA based Volume Ray-Casting (vrc_2017_final_2)
This paper outlines how a compute-intensive algorithm can be implemented on a FPGA card with a PCI Express interface, utilising Vivado HLS and Alpha Data’s ADB3 PCIe Bridge. The presented system is shown to be scalable and power efficient.
The FPGA platform is built from a combination of a top-level IP Integrator (IPI) system, IP cores for on/off-chip data flow and board-specific host communications. These are combined with the ray-casting IP cores written in C++ and synthesised with Xilinx’s Vivado HLS tool. Some important aspects of these IP are discussed.
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