V2.0 : 9 May 2017
The RD-KU3 provides a fully functional PCI Express Bridge interface with direct slave and DMA engine driven user interfaces, memory management interface and initial external IO interfaces for 40G Ethernet and SATA.
The reference design includes:
- Example "getting started" projects for Vivado IP Integrator.
- PCIe Backend IP core encrypted netlist, including high-performance scatter-gather DMA engines
- Board management and monitoring VHDL source code
- Comprehensive host device drivers for Linux and Windows 7
- Linux and Windows 7-64 bit edition API
- Bit-file reference design for SODIMM
- Reference design to demonstrate 10G Ethernet PHY connectivity
Also included is access to the Alpha Data Support download lounge for latest updates.
Note: RD-KU3 is not required if the intended for Xilinx SDAccel development.
Comes with RD-KU3
Standalone SODIMM Test FPGA Design
Register Access FPGA Design
DMA Demonstration FPGA Design
IBERT FPGA Design
Host Interface to SODIMMs Example FPGA Design
SFP+/QSFP+ IBERT Loopback Demo
Basic 10G/25G loopback test for SFP+/QSFP using pseudo random tester
SFP+/QSFP 10GE XGMII Loopback Demo
10G XGMII to SFP+/QSFP tester
QSFP+ 40GE XGMII Loopback Demo
40G XGMII to QSFP tester
SATA MAC IP and example PHY
Low Level SATA controller design
Dual-PCIE core Demo
Dual PCI Express End Point system
|Getting Started Block Diagrams|
Basic PCIe Block Diagram Demo
Simple PCI Express End Point with memory mapped interface
SDRAM PCIe Block Diagram Demo
Simple PCI Express End Point attached to onboard memory
✔ - Available
↺ - In Development
Alpha Data also provide initial email and telephone support for these products. Long term support can also be purchased as well as design services.