There are a number of design flows that can be used to create your final system:
Hardware designed using VHDL/Verilog HDLs, using the Alpha Data Reference Design IP and incorporating third party (i.e. Xilinx) IP modules. Synthesis, Place and Route performed by Xilinx Vivado tools.
Software written in C using the Alpha Data SDK API.
Using the Xilinx SDx family of design tools everything is designed with the tools using C++ and/or OpenCL along with IP modules.
The Coherent Accelerator Processor Interface (CAPI) design flow removes the need for the designer to develop their host interface as this is provided as a pre-built Power Server Layer (PSL) module.
The majority of the design uses Hardware Definition Languages (VHDL/Verilog) and C/C++ for the software.
Alpha Data also provide initial email and telephone support for these products. Long term support can also be purchased as well as design services.