Alpha Data CL3 Development Kit

Version 3.1 July 2017

With the high resolution and frame rates of modern video cameras it has become essential that the raw video stream is processed in hardware prior to being transferred to software for final image processing. To facilitate this Alpha Data continues to develop both hardware interfaces for various camera protocols and extend the software development Kit (CL3) to handle the heavy lifting requirements such as frame capture and store, region of interest windowing and frame transfer to the host system.

CL3 Data Flow Block Diagram

Alpha Data ADB3 FPGA board


CL3 Data Flow Block Diagram

Alpha Data Zynq SoC board

In many systems there may be multiple cameras, as shown above, and the CL3 can run multiple camera video streams (limited by the number of ports on the camera interface modules).

CL3 Data Flow Block Diagram 2

Basic CL3 System

Camera Interface Modules Supported by CL3









The CL3 Development Kit Overview

Hardware Layer

This layer provides connectivity between imaging devices, the Target FPGA and the host system. The Target FPGA can be used by developers to perform their desired image processing task. In addition to the Target, most Alpha Data re-configurable co-processors devices have a Bridge chip. This provides a connection to the Host system running the Software Layer. On Alpha Data devices without Bridge chips a Bridge core (normally PCIe) can be directly included in the Target FPGA. Implementation details of this are Alpha Data device specific.

The Hardware Layer of the SDK should be used for as much computational intense processing of the input image stream(s) as possible. In the developer's application it may be the case that acquisition of images by the Host is not necessary. However, for debugging, it is recommend that the developer keeps this capability provided by the example designs (before any processing is performed) so that verification of acquisition of the raw image can be performed.

Simple Frame Manipulation Functionality

  • Full frame capture
  • Region of interest (RoI) capture
  • Pixel/data Packing
  • Frame time stamping

Configurable Camera Triggers

The CL3 provides user configurable camera trigger generators. Allowing the user to specify active times/repeat times and generate one off triggers for the camera to facilitate the capturing of single images.

Software Layer

The lowest level of interaction between the Hardware and Software Layers take place via a device driver, for example Alpha Data's ADB3 driver. The driver provides the means to monitor interrupts, access the target FPGA as a Direct Slave, and initiate DMA's between the Target FPGA's attached memory and the Host memory.

Above the driver level the CL3 SDK provides a C++ software API. This provides classes that can be used to interact with the Hardware Layer (via the driver). The CL3 API classes include the following functions:

  • Low level register reads/writes.
  • Managing the serial communication over Camera Link interfaces.
  • Setting regions of interest when capturing images.
  • Configuring the Camera Link IP to interface with a particular specification of camera.
  • Controlling a camera's CC lines.
  • Acquiring raw camera data from the Target FPGA to host memory.

In addition to the hardware interaction classes the CL3 API also provides several classes for converting image formats on the host, and saving image data to disk.

ADM-XRC-7Z1 xrm2-clink-mini cl3-mfb-db and cl3-mfb-full
xrm2-clink-mini-rx cl3-mfb-rx-db and cl3-mfb-rx-full
ADM-XRC-KU1 xrm2-clink-mini cl3-mfb-db and cl3-mfb-full
xrm2-clink-mini-rx cl3-mfb-rx-db and cl3-mfb-rx-full
ADM-XRC-7K1 xrm2-clink-mini cl3-mfb-db and cl3-mfb-full
xrm2-clink-mini-rx cl3-mfb-rx-db and cl3-mfb-rx-full
ADM-XRC-7V1 xrm2-clink-mini cl3-mfb-db and cl3-mfb-full
xrm2-clink-mini-rx cl3-mfb-rx-db and cl3-mfb-rx-full
xrm2-coaxpress cl3-mfb-cxp6
xrm2-coaxpress/r8 cl3-mfb-cxp8

Supported Hardware Combinations

User Augmentation

CL3 Data Flow Block Diagram 3

Simple User Image Processing Module

The CL3 system has been designed to facilitate the user adding their own proprietary image processing functions to the incoming image data stream. The interface provides all the image framing and data signals required. There are also interfaces for the user to read and write control registers for the module from the host system and allow the module to access the onboard memory as a frame store.

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