- High Performance Reconfigurable Computing
- High Performance Reconfigurable Computing
SDRAM : 2GByte in 4 independent banks (512MBytes/bank) of DDR3 SDRAM @ DDR-1600.
Alternatively, 4Gbit devices can be fitted giving 4GByte on board in 4 banks of 1GByte
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Front IO
Up to 146 LVCMOS/LVDS I/O (programmable to 1.2, 1.5 or 1.8V)
8 High-Speed Serial Links
Rear IO
P1 : 1 PCIe data plane. 2 expansion planes, 2 100BASE-BX control planes, 8 GPIO
P2 : 64 IO compliant with VITA 46.9 X64S
SDRAM : 512MBytes in 2 independent banks (256MBytes/bank) of DDR3 SDRAM @ 1600MT/s (16-bit wide so 3.2GB/s).
Alternatively, slower 2Gbit devices can be fitted giving 1GByte on board in 2 banks of 512MByte @ 800MT/sec
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Front IO
Up to 146 LVCMOS/LVDS I/O
Programmable signaling levels of 1.5V, 1.8V or 2.5V
Up to 8 High-Speed Serial Links (two x4 Links Multiplexed between Front IO or Rear IO)
Rear IO
P1 : 1 PCIe data plane. 2 expansion planes, 2 100BASE-BX control planes, 8 GPIO
P2 : 64 IO compliant with VITA 46.9 X64S
SDRAM : 1GByte in 4 independent banks (2GByte option) of DDR3 SDRAM @ 800MT/s (32-bit wide so 3.2GB/s)
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Front IO
Up to 146 LVCMOS/LVDS I/O
Programmable signaling levels of 1.5V, 1.8V or 2.5V
8 High-Speed Serial Links
Rear IO
P1 : 1 PCIe data plane. 2 expansion planes, 2 100BASE-BX control planes, 8 GPIO
P2 : 64 IO compliant with VITA 46.9 X64S