Alpha Data Products Comparison by group : Fixed IO Boards

ADM-XRC-6T-DA1
Photo of the FPGA Board: Virtex-6 XMC  DDR3 SDRAM DACs ADCs

SDRAM : 1GByte in 4 independent banks (256Mbyte) of DDR-3 SDRAM 64M x 32-bits @ 400MHz

SDRAM : 2GByte in 4 independent banks (512Mbyte) of DDR-3 SDRAM 128M x 32-bits @ 400MHz option

FLASH : 4MByte serial Flash

FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.


Front IO

ADC [12-bit at 3.6GHz] x 1 or 2

DAC [14-bit at 2.5GHz] x 2

CLOCK x 2

TRIGGER x 2

Rear IO

8 High-Speed Serial Links via P15 connector (allowing second x4 PCI Express® channel from Target FPGA)

8 High-Speed Serial Links via P16 connector

38 LVTTL GPIO connections via P16 connector (VITA 46.9 X38S compatible pinout)


Option of P15 connector (Pseudo-XMC) providing High Speed Serial link to the carrier



ADM-XRC-6T-ADV8
Photo of the FPGA Board: Virtex-6 XMC JPEG2000 8x Codecs DDR3 SDRAM

SDRAM : 1GByte in 4 independent banks (2GByte/4GByte options) of DDR3 SDRAM @ 800MT/s (32-bit wide so 3.2GB/s)

FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.


Front IO

20 High-Speed Optical Receiver Links

Rear IO

8 High-Speed Serial Links via P15 connector (allowing second x4 PCI Express® Gen 2 channel from FPGA)

8 High-Speed Serial Receive links via P16 Connector

12 High-Speed Serial Transmit links via P16 Connector

8 LVTTL GPIO connections via P16 connector


JPEG2000 Codecs - 8 ADV212 devices



Not recomended for new designs.

ADM-XRC-5T-DA1
Photo of the FPGA Board: Virtex-5 PMC Analog DDR2 SDRAM Analog IF

SDRAM : 512MByte in 2 independent banks of DDR-II SDRAM 4M x 32-bits @ 333MHz

SSRAM : 8MByte in 2 independent banks of DDR-II SSRAM 2M x 18-bits @ 200MHz

FLASH : 4MByte serial Flash

FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.


Front IO

ADC [8-bit at 3GHz] x 1

DAC [12-bit at 2.3GHz] x 1

CLOCK x 1

I/O x 1

Rear IO

24 I-O connections via PMC Pn4 connector

(12 LVDS pairs) programmable signaling levels of 2.5V or 3.3V

8 High-Speed Serial Links via P15 connector

Only if the "extra connector fitted" option is chosen


Option of P15 connector (Pseudo-XMC) providing High Speed Serial link to the carrier



ADM-XRC-5T2-ADV6
Photo of the FPGA Board: Virtex-5 PMC JPEG2000 CodecsDDR2 SDRAM, I/O

SDRAM : 1Gbyte in 4 independent banks of DDR-II SDRAM 2 x 64M x 32-bits @ 333MHz

SSRAM : 8MByte in 2 independent banks of DDR-II SSRAM 2M x 18-bits @ 200MHz

FLASH : 4MByte serial Flash

FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.


Front IO

8 High-Speed Serial Links via 2 FCN Connectors (x4 Infiniband type)

Rear IO

32 I/O connections via PMC Pn4 connector

8 High-Speed Serial Links via P15 connector - Only if the "extra connector fitted" option is chosen


JPEG2000 Codecs - 6 ADV212 devices

Dual FCN Connections

Option of P15 connector (Pseudo-XMC) providing High Speed Serial link to the carrier






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