SDRAM : 8GBytes in 4 independent banks of DDR4 SDRAM (2400 MT/S)
FLASH : 2x QSPI serial NOR Flash
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Up to 146 LVCMOS/LVDS I/O (programmable to 1.2, 1.5 or 1.8V)
Up to 8 High-Speed Serial Links
Up to 10 High-Speed Serial Links via Pn6 connector, Standard build has 9 TX/RX data capable links and one external clock input. There is a build option available to use the external clock input as a 10th TX/RX data link.
Multiple LVCMOS 3.3V GPIO connections via Pn6 connector (VITA 46.9 X8d+X12d+X38s compatible pinout)
Multiple LVCMOS/LVDS GPIO connections via optional PMC Pn4 connector (1.8V levels with 2.5V compatible inputs)