SDRAM : Up to 1GByte in 2 independent banks (2G in 4 banks for LX330T, SX240T and FX200T) of DDR-II SDRAM @ 333MHz
SSRAM : 8MByte in 2 independent banks of DDR-II SSRAM 2M x 18-bits @ 200MHz
FLASH : 4MByte serial Flash
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Front IO
Up to 146 LVTTL/LVDS I/O
Programmable signaling levels of 1.8V, 2.5V or 3.3V
8 High-Speed Serial Links
Rear IO
64 I/O connections via PMC Pn4 connector
Programmable signaling levels of 2.5V or 3.3V
8 High-Speed Serial Links via P15 connector
Only if the "extra connector fitted" option is chosen
Option of P15 connector (Pseudo-XMC) providing High Speed Serial link to the carrier
SDRAM : Up to 1GByte in 2 independent banks of DDR-II SDRAM @ 333MHz
SSRAM : 4MByte DDR-II SSRAM 2M x 18-bits @ 200MHz
FLASH : 4MByte serial Flash
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Front IO
Up to 146 LVTTL/LVDS I/O
Programmable signaling levels of 1.8V, 2.5V or 3.3V
8 High-Speed Serial Links
Rear IO
64 I/O connections via PMC Pn4 connector
Programmable signaling levels of 2.5V or 3.3V
8 High-Speed Serial Links via P15 connector
Only if the "extra connector fitted" option is chosen
Option of P15 connector (Pseudo-XMC) providing High Speed Serial link to the carrier
ZBT : 48MByte of ZBT SRAM in 6 independent banks (2Mx36 each)
FLASH : 4MByte serial Flash
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Front IO
Up to 146 LVTTL/LVDS I/O
Programmable signaling levels of 1.8V, 2.5V or 3.3V
8 High-Speed Serial Links
Rear IO
6 I/O connections via PMC Pn4 connector
Fixed signaling level of 3.3V
8 High-Speed Serial Links via P15 (pseudo-XMC) connector - Only if the "Extra Connector fitted" option is chosen
Option of P15 connector (Pseudo-XMC) providing High Speed Serial link to the carrier
SDRAM : Up to 2GByte in 4 independent banks of DDRII SDRAM @ 333MHz
FLASH : 4MByte serial Flash (connected to user FPGA)
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Front IO
Up to 146 LVTTL/LVDS I/O
Programmable signaling levels of 1.8V, 2.5V or 3.3V
Rear IO
64 I/O connections via PMC pn4 connector
Not recomended for new designs.
ADC-VXSSDRAM : 1GByte in 4 independent banks of DDR-II SDRAM (64M x 32-bits each) @ 333MHz
FLASH : 2 x 4MByte serial Flash
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Front IO
4 - x4 SFP modules or x4 HSSDC2 connectors
Rear IO
110 I/O connections from Pn4 to VME P2 (VITA 35 compliant)
x8 Links to P0 connector. High speed switching to XMC sites or on board Virtex-5 devices.
Provides sites for 2 PMC boards as well as onboard FPGA sites.