- High Performance Reconfigurable Computing
- High Performance Reconfigurable Computing
SDRAM : 2GByte in 4 independent banks (512MBytes/bank) of DDR3 SDRAM @ DDR-1600. 4GByte option available
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Front IO
High Pin Count (HPC) FMC Standard Connector:
GPIO 80 pairs
GTX Links x10
Rear IO
P1 : 1 data plane. 2 expansion planes, 2 control planes, and 2 additional MGT lanes
P2 : 32 GPIO and 10 transceiver lanes compliant to VITA 46.9 X24S+X12D+X8D
Rear Transition Module (RTM) available to accelerate development by providing monitor and control access to all Rear (backplane) IO signals.
SDRAM : 2GByte in 4 independent banks (512MBytes/bank) of DDR3 SDRAM @ DDR-1600.
Alternatively, 4Gbit devices can be fitted giving 4GByte on board in 4 banks of 1GByte
or 8Gbit devices can be fitted giving 8GByte on board in 4 banks of 2GByte
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Front IO
Up to 146 LVCMOS/LVDS I/O (programmable to 1.2, 1.5 or 1.8V)
8 High-Speed Serial Links
Rear IO
Up to 10 High-Speed Serial Links via Pn6 connector
38 LVCMOS 3.3V GPIO connections via Pn6 connector (VITA 46.9 X8d+X12d+X38s compatible pinout)
64 LVCMOS/LVDS GPIO connections via optional PMC Pn4 connector (1.8V levels with 2.5V compatible inputs)
SDRAM : 512MBytes in 2 independent banks (256MBytes/bank) of DDR3 SDRAM @ 1600MT/s (16-bit wide so 3.2GB/s).
Alternatively, slower 2Gbit devices can be fitted giving 1GByte on board in 2 banks of 512MByte @ 800MT/sec
FLASH : Configuration Flash providing an initialisation design for automatic loading into the target FPGA.
Front IO
Up to 146 LVCMOS/LVDS I/O
Programmable signaling levels of 1.5V, 1.8V or 2.5V
Up to 8 High-Speed Serial Links (two x4 Links Multiplexed between Front IO or Rear IO)
Rear IO
Up to 8 High-Speed Serial Links via Pn6 connector (two x4 Links Multiplexed between Front IO or Rear IO)
There is a build option for a 10/100/1000 Ethernet Interface to be fitted which connects to P6 (replaces one x4 high speed serial link)
38 LVCMOS/LVDS GPIO connections via Pn6 connector (VITA 46.9 X38s compatible pinout)
64 LVCMOS/LVDS GPIO connections via optional PMC Pn4 connector (2.5V levels with 3.3V compatible inputs)