ADA-VPX3-KU1 - Radar/Sonar Beamforming


Photo 1 of ada-vpx3-ku1Photo 2 of ada-vpx3-ku1Photo 3 of ada-vpx3-ku1Main Photo of ada-vpx3-ku1  Board: FPGA COTS board: Xilinx Kintex Ultrascale, 3U VPX, Ethernet, SATA : Comm, Mil Kintex UltraSCALE

ADA-VPX3-KU1 Documents

Datasheet v1.0 (pdf)

Support and Development Kit

For more details on the ADM-XRC Gen 3 SDK and ADB3 Driver see the ADM-XRC Gen 3 SDK Page.

Contact Alpha Data support if you have any problems or questions.

Windows SDK: v1.7.0 (1 Dec 2014)

Linux SDK: v1.7.0 (1 Dec 2014)

Windows Driver: v1.4.19 (8 Oct 2018)

Linux Driver: v1.4.19 (8 Oct 2018)


  • Radar/Sonar Beamforming
  • Image/Video Processing
  • Digital Signal Processing
  • Data Encryption

Board Features

  • Xilinx Kintex Ultrascale XCKU060 FPGA
  • Customised conduction-cooled heatplate
  • Air-Cooled/Conduction-Cooled Options
  • Separate PCI Express Bridge
  • XRM2 I/O Interface
  • COTS Product
  • 3U VPX (OpenVPX Compliant)

FPGA Features (Hard IP)

  • 3x PCI Express Gen3 x8 cores (6 for XCKU115)


The ADA-VPX3-KU1 assembly is based on the Xilinx Kintex UltraScale range of Platform FPGAs, bringing together the power and configurability of the ADM-XRC-KU1 FPGA module in a 3U VPX format.

Features include PCI Express Gen2 interface, external memory, high density I/O, system monitoring and flash boot facilities.

A comprehensive cross platform API with support for Microsoft Windows, Linux and VxWorks provides access to the full functionality of these hardware features.

Placing the PCI Express bridge in bypass allows the creation of a Gen 2 x8 PCI Express endpoint design directly into the target FPGA. Target FPGAs KU060 and KU115 can also support Gen3 x8 PCI Express designs.

The conduction-cooled variant uses a single-piece heatplate, profiled to match both the carrier and FPGA boards and provide optimal cooling performance.

Board Format

3U VPX (OpenVPX Compliant)

Environmental Specifications

Temperature Limits:

CodeCooling OptionOperating Temp.Storage Temp.
AC0Air Cooled Commercial0°C+55°C-40°C+85°C
AC1Air Cooled Industrial-40°C+70°C-55°C+100°C
CC1Conduction Cooled Industrial-40°C+70°C[1]-55°C+100°C
[1] - with high-efficiency system cooling this can be raised to 85°C - Contact Alpha Data for more details

Conformal Coating Options:

Acrylic or Polyurethane

Contact sales for specification of coatings.

Operating Humidity range:

Up to 95% (non-condensing)

EMC Conformity:

FCC 47CFR Part 2
EN55022:2010 Equipment ClassB

For more information on the operating conditions for the different cooling options go to: Alpha Data Environmental Specification Page.

Or read: Alpha Data Environment Specification (PDF).

Host I/F

PCI Express® Gen2 x1, x2 or x4 link to separate bridge device with 2GB/s local link to user FPGA. 4 DMA Controllers. Interrupt Controller

Target FPGA Device

Xilinx Kintex® Ultrascale

XCKU060 XCKU115 - FLVA1517

FPGA Outline Specifications

20nm ASIC-class system-level performance with up to 2X Greater System Performance/Watt

Fabric clock FMAX = 725MHz

GTH max line rate = 16.375 Gb/s

LVDS max rate = 1600Mb/s

FPGA Resources

Chosen DeviceFFsLUTsDSPsBRAM

FPGA Hard IP Cores

  • 3x PCI Express Gen3 x8 cores (6 for XCKU115)

On Board Memory

Memory TypeNo. BanksMemory Size (per bank)

Target FPGA Configuration

  • By PCI Express Bridge on power up
  • By software via PCI Express Bridge
  • Via External JTAG connector

FPGA Configuration Flash

Flash TypeFlash SizeDescription
BPI1GBit2x Bridge, 2x Target, 1x VPD Data Zone
each of 32Mb (bridge) 386Mb (Target)

On-board Clock Specifications

  • Low-jitter 250MHz reference clock, suitable for SerDes applications
  • Low-jitter 200MHz reference clock for IOB delay circuits
  • Custom clock inputs available through the XRM2 interface
  • Two Software-Programmable Clocks

I/O Interfaces

Interface TypeQtyDescription
Discrete146LVCMOS/LVDS I/O (programmable to 1.2, 1.5 or 1.8V) to XRM2
Serial Links
8High-Speed Serial Links to XRM2
REAR I/O (Pn6)
Serial Links
10High-Speed Serial Links via Pn6 connector, Standard build has 9 TX/RX data capable links and one external clock input. There is a build option available to use the external clock input as a 10th TX/RX data link.
Discrete I/O38LVCMOS 3.3V GPIO connections via Pn6 connector (VITA 46.9 X8d+X12d+X38s compatible pinout)
REAR I/O (Pn4)
Discrete I/O64Multiple LVCMOS/LVDS GPIO connections via optional PMC Pn4 connector (1.8V levels with 2.5V compatible inputs)
Note: only available with Pn4 Build Option selected


The ADA-VPX3-KU1 is supplied with the ADMXRCG3 Support & Development kit (SDK) along with ADB3 Driver for Windows / Linux / VxWorks. (see left)

Ordering Code
ParametercodeParameter Description
Kintex Ultrascale devicez

KU060 = XCKU060 FPGA fitted,
KU115 = XCKU115 FPGA fitted

Pn4 Fittedp

blank = not fitted,
/Pn4 = Pn4 connector fitted


blank = air cooled commercial,
/AC1 = air cooled industrial,
/CC1 = conduction cooled industrial

Conformal coatinga

blank = no conformal coating,
A = Acrylic,
P = Polyurethane

IO OptionIO

blank = One differential pair on Pn6 designated as an external clock input,
/10RX = External clock input replaced by 10th data input

Contact sales for other ordering options


  • ADA-VPX3-KU1 Assembly
  • One Year Warranty
  • One Year Technical Support

Sales Questions

For any sales questions regarding the ADA-VPX3-KU1, please e-mail us at:

Technical Support

For any technical questions regarding Alpha-Data products please e-mail us at:

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