Support and Development Kit
For more details on the ADM-XRC Gen 3 SDK and ADB3 Driver see the ADM-XRC Gen 3 SDK Page.
Contact Alpha Data support if you have any problems or questions.
FPGA Features (Hard IP)
The ADA-VPX3-KU1 assembly is based on the Xilinx Kintex UltraScale range of Platform FPGAs, bringing together the power and configurability of the ADM-XRC-KU1 FPGA module in a 3U VPX format.
Features include PCI Express Gen2 interface, external memory, high density I/O, system monitoring and flash boot facilities.
A comprehensive cross platform API with support for Microsoft Windows, Linux and VxWorks provides access to the full functionality of these hardware features.
Placing the PCI Express bridge in bypass allows the creation of a Gen 2 x8 PCI Express endpoint design directly into the target FPGA. Target FPGAs KU060 and KU115 can also support Gen3 x8 PCI Express designs.
The conduction-cooled variant uses a single-piece heatplate, profiled to match both the carrier and FPGA boards and provide optimal cooling performance.
3U VPX (OpenVPX Compliant)
|Code||Cooling Option||Operating Temp.||Storage Temp.|
|AC0||Air Cooled Commercial||0°C||+55°C||-40°C||+85°C|
|AC1||Air Cooled Industrial||-40°C||+70°C||-55°C||+100°C|
|CC1||Conduction Cooled Industrial||-40°C||+70°C||-55°C||+100°C|
| - with high-efficiency system cooling this can be raised to 85°C - Contact Alpha Data for more details|
Conformal Coating Options:
Acrylic or Polyurethane
Contact sales for specification of coatings.
Operating Humidity range:
Up to 95% (non-condensing)
FCC 47CFR Part 2
EN55022:2010 Equipment ClassB
For more information on the operating conditions for the different cooling options go to: Alpha Data Environmental Specification Page.
Or read: Alpha Data Environment Specification (PDF).
PCI Express® Gen2 x1, x2 or x4 link to separate bridge device with 2GB/s local link to user FPGA. 4 DMA Controllers. Interrupt Controller
Target FPGA Device
Xilinx Kintex® Ultrascale
XCKU060 XCKU115 - FLVA1517
FPGA Outline Specifications
20nm ASIC-class system-level performance with up to 2X Greater System Performance/Watt
Fabric clock FMAX = 725MHz
GTH max line rate = 16.375 Gb/s
LVDS max rate = 1600Mb/s
FPGA Hard IP Cores
On Board Memory
|Memory Type||No. Banks||Memory Size (per bank)|
Target FPGA Configuration
FPGA Configuration Flash
|Flash Type||Flash Size||Description|
|BPI||1GBit||2x Bridge, 2x Target, 1x VPD Data Zone|
each of 32Mb (bridge) 386Mb (Target)
On-board Clock Specifications
|FRONT I/O (XRM2)|
|Discrete||146||LVCMOS/LVDS I/O (programmable to 1.2, 1.5 or 1.8V) to XRM2|
|8||High-Speed Serial Links to XRM2|
|REAR I/O (Pn6)|
|10||High-Speed Serial Links via Pn6 connector, Standard build has 9 TX/RX data capable links and one external clock input. There is a build option available to use the external clock input as a 10th TX/RX data link.|
|Discrete I/O||38||LVCMOS 3.3V GPIO connections via Pn6 connector (VITA 46.9 X8d+X12d+X38s compatible pinout)|
|REAR I/O (Pn4)|
|Discrete I/O||64||Multiple LVCMOS/LVDS GPIO connections via optional PMC Pn4 connector (1.8V levels with 2.5V compatible inputs)|
Note: only available with Pn4 Build Option selected
The ADA-VPX3-KU1 is supplied with the ADMXRCG3 Support & Development kit (SDK) along with ADB3 Driver for Windows / Linux / VxWorks. (see left)
|Kintex Ultrascale device||z|
KU060 = XCKU060 FPGA fitted,
blank = not fitted,
blank = air cooled commercial,
blank = no conformal coating,
blank = One differential pair on Pn6 designated as an external clock input,
|Contact sales for other ordering options|
For any sales questions regarding the ADA-VPX3-KU1, please e-mail us at:
For any technical questions regarding Alpha-Data products please e-mail us at:
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