XRM2-ADC-S4/3G - IF/Baseband Signal Sampling



  • IF/Baseband Signal Sampling

Board Features

  • Single 8-bit 3Gsps ADC
  • External Clock Input
  • Thermal monitoring of the ADCs
  • Alpha Data XRM2 I/O Module


The XRM2-ADC-S4/3G is an XRM2 I/O Module, providing one Analog to Digital converter with 8-bit resolution and sampling rates up to 3Gsps.

Aimed at IF/Baseband Signal Sampling, the sampling clock can be sourced from either an external clock source or from a clock generated within the attached FPGA board. An Auxiliary I/O port is provided for use as a trigger control or for general purpose signaling. An additional two ports are available for use as high-speed interconnect between boards for synchronisation.

The built-in thermal monitor allows the user to check the operating temperature of the ADC. Provided as part of the sample design is the functionality to read the temperature of the device, and software to monitor this and recalibrate the ADC if the thermal drift is sufficient. The software will also shut the ADC down if the device starts to go over the maximum operating temperature.

Board Format

Alpha Data XRM2 I/O Module

Environmental Specifications

Temperature Limits:

CodeCooling OptionOperating Temp.Storage Temp.
AC0Air Cooled Commercial0°C+55°C-40°C+85°C

Operating Humidity range:

Up to 95% (non-condensing)

EMC Conformity:

FCC 47CFR Part 2
EN55022:2010 Equipment ClassB

For more information on the operating conditions for the different cooling options go to: Alpha Data Environmental Specification Page.

Or read: Alpha Data Environment Specification (PDF).

I/O Interfaces

Interface TypeQtyDescription
ANALOG I/O (Front Panel)
ADC1Single Analog to Digital Converter
Resolution: 8-bit
Max Clock Rate: 3Gsps
Impedance: 50Ω
Levels: Range1: ±410 mV nominal|Range2: ±300 mV nominal
Connector: SMA
Range selectable via FPGA and ADC serial port: bandwidth limited by input transmission-line transformers.
ADC 3dB bandwidth 3GHz.
Note: exceeding the maximum signal limit may result in permanent degradation of converter performance.
DISCRETE I/O (Front Panel)
External clock input1External clock input
Max Clock Rate: 1500MHz
Bandwidth: 200MHz to 1500MHz, single edge sampling 500MHz to 1500MHz, dual edge sampling
Impedance: 50Ω (AC coupled)
Levels: -6dBm to +12dBm (nominal 0 dBm)
Connector: SMA
External clock output1External clock output
Max Clock Rate: 1500MHz
Bandwidth: 25MHz to 1500MHz
Impedance: 50Ω (AC coupled)
Levels: 0 dBm nominal (adjustable)
Connector: SMA
Source: GTP or User Clock from XRC board.
Auxiliary I/O1Auxiliary I/O
Impedance: input 4k7Ω (DC coupled)
Levels: +3V3 LVTTL
Connector: SMA
DISCRETE I/O (PCB Connector)
Synchronisation I/O2Synchronisation I/O
Levels: 1V8 Logic (DC coupled)
Connector: U.FL - Limited Access in assembled system
User configurable as inputs or outputs, signals direct to FPGA pins (Vccfpio).
Note: signals on these connectors must be restricted to 1V8 logic otherwise damage may result.


Example UCF, HDL files and Application software are provided with the board.

Ordering Code
ParametercodeParameter Description

blank = No Heastink,
/HTSK-XRM-ADC-HS-1 = Heatsink Fitted

Contact sales for other ordering options


  • XRM2-ADC-S4-3G Board
  • One Year Warranty
  • One Year Technical Support

Sales Questions

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Technical Support

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