XRM2-ADC-D7/500 - IF/Baseband Signal Sampling



  • IF/Baseband Signal Sampling

Board Features

  • Dual 12-bit 500Msps ADCs
  • External Clock Input
  • Alpha Data XRM2 I/O Module


The XRM2-ADC-D7/500 is an XRM2 I/O Module, providing two Analog to Digital converters with 12-bit resolution and sampling rates up to 500Msps

Aimed at IF/Baseband Signal Sampling, the sampling clock can be sourced from either an external clock source or from a clock generated within the attached FPGA board. A Trigger I/O port is provided for use as a trigger control and an Auxiliary I/O port for general purpose signaling. An additional two ports are available for use as high-speed interconnect between boards for synchronisation.

Board Format

Alpha Data XRM2 I/O Module

Environmental Specifications

Temperature Limits:

CodeCooling OptionOperating Temp.Storage Temp.
AC0Air Cooled Commercial0°C+55°C-40°C+85°C

Operating Humidity range:

Up to 95% (non-condensing)

EMC Conformity:

FCC 47CFR Part 2
EN55022:2010 Equipment ClassB

For more information on the operating conditions for the different cooling options go to: Alpha Data Environmental Specification Page.

Or read: Alpha Data Environment Specification (PDF).

I/O Interfaces

Interface TypeQtyDescription
ANALOG I/O (Front Panel)
ADC2Dual Analog to Digital Converters
Resolution: 12-bit
Max Clock Rate: 500Msps
Impedance: 50Ω
Levels: +12 dBm (2.5 Vppk =ADC full scale)
Connector: SMA
DISCRETE I/O (Front Panel)
External clock input1External Clock Input
Bandwidth: 80MHz to 1500MHz
Impedance: 50Ω - AC coupled
Levels: -6dBm to +12 dBm (nominal 0 dBm)
Connector: SMA
Trigger I/O1Trigger I/O
Impedance: 4k7Ω (DC coupled)
Levels: +3V3 LVTTL
Connector: SMA
Auxiliary I/O1Auxiliary I/O
Impedance: 4k7Ω (DC coupled)
Levels: +3V3 LVTTL
Connector: SMA


Example UCF, HDL files and Application software are provided with the board.

Ordering Code


  • XRM2-ADC-D7-500 Board
  • One Year Warranty
  • One Year Technical Support

Sales Questions

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Technical Support

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