ADM-PCIE-9V3

Summary

The ADM-PCIE-9V3 is a half-length, low profile, PCI Express Add-In Card featuring the powerful and efficient Xilinx Virtex UltraScale Plus VU3P-2 FPGA.

16 lane PCIe Gen3 or 8 lane PCIe Gen4 capable Interface.

Front IO with 2x QSFP28 sockets, each supporting one 100GbE or four 25GbE interfaces. Onboard Ultraport SlimSAS Connector for OpenCAPI Connectivity.
Two 1G x72 DDR4-2400 ECC memory banks each provide 8GiB of on-board DDR4-2400 memory (72 bits wide).

System monitoring of temperature, voltage, and current gives developers accurate feedback of power utilization for their designs.
This card comes with low-profile and full-height front brackets (low-profile bracket fitted as standard) and an optional blower for low air-flow systems.

Specification

Board Format

Environmental Specifications

Operating Humidity Range:
Up to 95% (non-condensing)

EMC:

EMC Directive 2014/30/EU
55022:2010
55032:2015
55024:2010 + A1:2015
55035:2017
EN 61000-3-3:2014
EN 61000-3-3:2013

Additional Declarations:
FCC/CFR 47: Part 15: 2016 Radiated Emissions (to 40GHz) Conducted Emissions ANSI C63.4:2014, Class A

Other Certifications:
KN32 Class A
KN35
VCCI (V-3/2014.04)
ICES-003:Issue 6
AS/NZS CISPR 22: 2009 + A1:2010
CISPR 22:2008
CISPR 32:2015, Class A

Host I/F

Target Device

Xilinx Virtex® UltraScale Plus™
XCVU3P-2 (FFVC1517)

FPGA Resources

FPGA Hard IP Cores

On Board Memory options

Other on-board memory

2kb I2C EEPROM - Non-volatile data storage for the user design (i.e. storing MAC addresses)

Board Management

The ADM-PCIE-9V3 houses a system monitoring chip which is able to provide real-time temperature, voltage and current readings of the system, as well as reconfigure programmable clocks and much more. The system monitor can be accessed directly through the USB interface via the front panel, the UART connection to the target FPGA or through the SMBus interface on the card's PCI Express edge connector. When enabled**, IPMI can also be used to communicate with the system monitor, allowing for remote communication and management with the ADM-PCIE-9V3.

** IPMI is disabled by default and should only be enabled when the board is installed in an IPMI compliant system. Please contact the factory for details on enabling IPMI on the ADM-PCIE-9V3.

Target FPGA Configuration

From onboard Flash
Through USB board management (built-in JTAG)
Partial Reconfiguration (via MCAP) Over PCI Express

FPGA Configuration Flash

High-Speed Network Interfaces

Ordering Information

Related Products

Resources

Product Change Notices

PCN-201704-1.2

Product Conformity

ADM-PCIE-9V3 UK Declaration of Conformity

ADM-PCIE-9V3 EU Declaration of Conformity

Reference Designs: (RD-9V3)

The RD-9V3 contains a suite of Vivado reference designs demonstrating how to use the board, including PCIe DMA examples, DDR4 memory, QPSI flash and GT IBERT example.

PCIe examples are compatible with the ADXDMA Driver and API.

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Open source OpenCAPI reference designs can be found for this board on GitHub.

Download Reference Designs [Purchase]

Download the ADXDMA Driver [Login Required]

Open source OpenCAPI reference designs can be found for this board on GitHub

Deliverables

ADM-PCIE-9V3 Board
One Year Warranty
One Year Technical Support
Xilinx Vivado Board Files

Support

Please contact Alpha Data for full details on the available support packages for the ADM-PCIE-9V3.