XRM2-ADC-D9/500 - IF/Baseband Signal Sampling

AD01252



Applications

  • IF/Baseband Signal Sampling

Board Features

  • Alpha Data XRM2 I/O Module
  • Dual 14-bit 500Msps ADCs
  • External Clock Input


Summary

The XRM-ADC-D9/500 is an XRM2 I/O Module, providing two Analog to Digital converters with 14-bit resolution at sampling rates up to 500Msps.

Aimed at IF/Baseband Signal Sampling, the sampling clock can be sourced from either an external clock source or from a clock generated within the attached FPGA board. An Auxiliary I/O port is provided for use as a trigger input and general purpose signaling. An additional two ports are available for use as high-speed interconnect between boards for synchronisation.


Board Format

Alpha Data XRM2 I/O Module


Environmental Specifications

Temperature Limits:

CodeCooling OptionOperating Temp.Storage Temp.
MinMaxMinMax
AC0Air Cooled Commercial0°C+55°C-40°C+85°C

Operating Humidity range:

Up to 95% (non-condensing)

EMC Conformity:

FCC 47CFR Part 2
EN55022:2010 Equipment ClassB

For more information on the operating conditions for the different cooling options go to: Alpha Data Environmental Specification Page.

Or read: Alpha Data Environment Specification (PDF).


I/O Interfaces

Interface TypeQtyDescription
ANALOG I/O (Front Panel)
ADC2Dual Analog to Digital Converters
Resolution: 14-bit
Max Clock Rate: 500Msps
Impedance: 50Ω
Levels: +10dBm
Connector: SSMC
Note: exceeding the maximum signal limit may result in permanent degradation of converter performance.
DISCRETE I/O (Front Panel)
External clock input1External Clock Input
Max Clock Rate: 80MHz to500Mhz
Impedance: 50Ω
Levels: -6dBm to +12 dBm (nominal 0 dBm)
Connector: SSMC
Note: Exceeding the maximum voltage limit may result in permanent degradation of converter
Auxiliary I/O2Auxiliary I/O
Impedance: 4k7Ω (DC Coupled)
Levels: +3V3 Logic (DC coupled)
Connector: SSMC
User configurable as inputs or outputs, signals direct to FPGA pins.
Note: signals on these connectors must be restricted to 2V5 logic otherwise damage may result.
DISCRETE I/O (PCB Connector)
Synchronisation I/O2Synchronisation I/O
Levels: 1V8 Logic (DC coupled)
Connector: U.FL - Limited Access in assembled system
User configurable as inputs or outputs, signals direct to FPGA pins (Vccfpio).
Note: signals on these connectors must be restricted to 1V8 logic otherwise damage may result.

Software

Example UCF, HDL files and Application software are provided with the board.


Ordering Code
XRM2-ADC-D9/500

Deliverables

  • XRM2-ADC-D9-500 Board
  • One Year Warranty
  • One Year Technical Support


Sales Questions

For any sales questions regarding the XRM2-ADC-D9/500, please e-mail us at:

sales@alpha-data.com


Technical Support

For any technical questions regarding Alpha-Data products please e-mail us at:

support@alpha-data.com








©2019 Alpha Data Parallel Systems - All rights reserved