The XRM-ADC-D9/500 is an XRM2 I/O Module, providing two Analog to Digital converters with 14-bit resolution at sampling rates up to 500Msps.
Aimed at IF/Baseband Signal Sampling, the sampling clock can be sourced from either an external clock source or from a clock generated within the attached FPGA board. An Auxiliary I/O port is provided for use as a trigger input and general purpose signaling. An additional two ports are available for use as high-speed interconnect between boards for synchronisation.
Alpha Data XRM2 I/O Module
|Code||Cooling Option||Operating Temp.||Storage Temp.|
|AC0||Air Cooled Commercial||0°C||+55°C||-40°C||+85°C|
Operating Humidity range:
Up to 95% (non-condensing)
FCC 47CFR Part 2
EN55022:2010 Equipment ClassB
For more information on the operating conditions for the different cooling options go to: Alpha Data Environmental Specification Page.
Or read: Alpha Data Environment Specification (PDF).
|ANALOG I/O (Front Panel)|
|ADC||2||Dual Analog to Digital Converters|
Max Clock Rate: 500Msps
Note: exceeding the maximum signal limit may result in permanent degradation of converter performance.
|DISCRETE I/O (Front Panel)|
|External clock input||1||External Clock Input|
Max Clock Rate: 500Mhz
Levels: +3V3 LVTTL
Note: Exceeding the maximum voltage limit may result in permanent degradation of converter
|Auxiliary I/O||2||Auxiliary I/O|
Impedance: 4k7Ω (DC Coupled)
Levels: 2V5 Logic (DC coupled)
User configurable as inputs or outputs, signals direct to FPGA pins.
Note: signals on these connectors must be restricted to 2V5 logic otherwise damage may result.
Example UCF, HDL files and Application software are provided with the board.
For any sales questions regarding the XRM2-ADC-D9/500, please e-mail us at:
For any technical questions regarding Alpha-Data products please e-mail us at:
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