- High Performance Reconfigurable Computing
- High Performance Reconfigurable Computing
AD01336
Applications
Board Features
Summary
The FMC-DA4 is an FMC I/O Module, providing two Analog to Digital converters with 14-bit resolution and sampling rates up to 3Gsps, and two Digital to Analog converters with 16-bit resolution and sampling rates up to 2.5Gsps.
The FMC-DA4 is a VITA 57.1 compliant single width HPC FMC module, designed for use with Alpha Data's VITA 57.1 compliant carrier cards. It provides the user with dual high speed Analog to Digital Converters at 14bits/3GHz and dual high speed Digital to Analog converters at 16bits/2.5GHz along with an external clock input and clock output and a number of bidirectionl trigger/synchronisation signals.
Power Consumption ( 3GHz sampling, both ADC channels, 2GHz sampling both DAC channels) 25W, conduction cooled
On-board temperature monitoring
Requires FPGA speed grades of -2 or better to support 12.5 Gbps operation of serial links.
Board Format
VITA 57.1 FPGA Mezzanine Card (FMC)
Environmental Specifications
Temperature Limits:
| Code | Cooling Option | Operating Temp. | Storage Temp. | ||
|---|---|---|---|---|---|
| Min | Max | Min | Max | ||
| CC1 | Conduction Cooled Industrial | -40°C | +70°C[1] | -55°C | +100°C |
| [1] - with high-efficiency system cooling this can be raised to 85°C - Contact Alpha Data for more details | |||||
Operating Humidity range:
Up to 95% (non-condensing)
EMC Conformity:
FCC 47CFR Part 2
EN55022:2010 Equipment ClassB
For more information on the operating conditions for the different cooling options go to: Alpha Data Environmental Specification Page.
Or read: Alpha Data Environment Specification (PDF).
I/O Interfaces
| Interface Type | Qty | Description |
|---|---|---|
| ANALOG I/O (Front Panel) | ||
| ADC | 2 | Dual Analog to Digital Converters Resolution: 14-bit Max Clock Rate: 330Msps to 3Gsps Impedance: 50Ω Levels: ADC full scale input range is programmable from +10dBm to -10 dBm in 1 dB steps Connector: SSMC or MCX Dual 14bit/3Ghz ADCs FSI Range adjustable in 1 dB steps The DAC and ADC clocks must have a integer ratio |
| DAC | 2 | Dual Digital to Analog Converters Resolution: 16-bit Max Clock Rate: 2.5Gsps Impedance: 50Ω Levels: Power: +1 dBm to -30 dBm Connector: SSMC or MCX Dual 16bit/2.5GHz DACs Programmable attenuation : to 31dB in 0.5 dB steps |
| DISCRETE I/O (Front Panel) | ||
| External clock input | 1 | External clock input Max Clock Rate: 3GHz Bandwidth: 10MHz to 3000MHz nominal Impedance: 50Ω Levels: -6 dBm to +12dBm (0dBm nominal) Connector: SSMC or MCX |
| External clock output | 1 | External clock output Max Clock Rate: 3GHz Bandwidth: 10MHz to 3000MHz nominal Impedance: 50Ω Levels: Power: nominal 0 dBm Connector: SSMC or MCX Note: Clock output shall echo fastest of the ADC/DAC clock, internal or external clock source. |
| Trigger I/O | 1 | Trigger I/O Impedance: 50Ω Levels: +3V3 or 5V Connector: SSMC or MCX |
| Auxiliary I/O | 1 | Auxiliary I/O Impedance: 50Ω Levels: +3V3 or 5V Connector: SSMC or MCX |
| Synchronisation IO | 1 | ADC Sync Signal Impedance: 50Ω Levels: 1V8 - direct input/output of the FPGA Connector: U.FL |
| DISCRETE I/O (PCB Connectors) | ||
| Synchronisation I/O | 2 | Bidirectional Fast IO Signals direct from FPGA. Impedance: Direct connection to FPGA Levels: +1V8 Connector: U.FL - Limited Access in assembled system |
Software
FMC Pinout available in User Manual
| Ordering Code | ||
|---|---|---|
| FMC-DA4 |
Deliverables
Sales Questions
For any sales questions regarding the FMC-DA4, please e-mail us at:
Technical Support
For any technical questions regarding Alpha-Data products please e-mail us at:
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