ADM-XRC-KU1 - Embedded Data Processing

AD01305


Photo 1 of adm-xrc-ku1Photo 2 of adm-xrc-ku1Photo 3 of adm-xrc-ku1Main Photo of adm-xrc-ku1  Board: COTS board: Xilinx Kintex UltraScale, XMC, DDR4 SDRAM, PCIE : Comm, Ind, Mil Kintex UltraSCALE

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ADM-XRC-KU1 Documents

Datasheet v1.1 (pdf)

User Manual v1.9 (pdf)

Support and Development Kit

For more details on the ADM-XRC Gen 3 SDK and ADB3 Driver see the ADM-XRC Gen 3 SDK Page.

Contact Alpha Data support if you have any problems or questions.

Windows SDK: v1.0.0 (31 Jan 2017)

Linux SDK: v1.0.0 (31 Jan 2017)

Windows Driver: v1.4.19 (8 Oct 2018)

Linux Driver: v1.4.19 (8 Oct 2018)





Applications

  • Embedded Data Processing
  • Radar/Sonar Beamforming
  • ELINT
  • Image/Video Processing
  • Digital Signal Processing
  • Data Encryption

Board Features

  • Xilinx Kintex UltraScale FPGA
  • XMC (Switched Mezzanine Card, VITA 42)
  • Air-Cooled/Conduction-Cooled Options
  • Separate PCI Express Bridge
  • XRM2 I/O Interface
  • COTS Product

FPGA Features (Hard IP)

  • 3x PCI Express Gen3 x8 cores (6 for XCKU115)


Summary

The ADM-XRC-KU1 is a high performance reconfigurable XMC (compliant to VITA Standard 42.0 and 42.3) based on the Xilinx Kintex Ultrascale range of Platform FPGAs.

Features include PCI Express Gen2 interface, external memory, high density I/O, system monitoring and flash boot facilities.

A comprehensive cross platform API with support for Microsoft Windows, Linux and VxWorks provides access to the full functionality of these hardware features.

Board management is provided by the combination of the Artix FPGA and AVR Microcontroller. This allows the board to be managed via PCI Express or via USB.

The KU1 provides multiple communications modes:

PCI Express Gen2 x4 through the Artix FPGA with an optional Gen3 x4 PCI Express link direct to the target FPGA.

Gen3 x8 PCI Express link direct to the target when the bridge is in USB mode.

An optional Gen3 x8 PCI Express link provided through Pn6 using a compatible XMC carrier.


Board Format

XMC (Switched Mezzanine Card, VITA 42)


Environmental Specifications

Temperature Limits:

CodeCooling OptionOperating Temp.Storage Temp.
MinMaxMinMax
AC0Air Cooled Commercial0°C+55°C-40°C+85°C
AC1Air Cooled Industrial-40°C+70°C-55°C+100°C
CC1Conduction Cooled Industrial-40°C+70°C[1]-55°C+100°C
[1] - with high-efficiency system cooling this can be raised to 85°C - Contact Alpha Data for more details

Conformal Coating Options:

Acrylic or Polyurethane

Contact sales for specification of coatings.

Operating Humidity range:

Up to 95% (non-condensing)

EMC Conformity:

FCC 47CFR Part 2
EN55022:2010 Equipment ClassB

For more information on the operating conditions for the different cooling options go to: Alpha Data Environmental Specification Page.

Or read: Alpha Data Environment Specification (PDF).


Host I/F

PCI Express® Gen2 x4 (Separate bridge FPGA) or Gen3 x8 (direct from Target FPGA)


Target FPGA Device

Xilinx Kintex® UltraScale™

XCKU060 XCKU115 - FLVA1517

FPGA Outline Specifications

20nm ASIC-class system-level performance with up to 2X Greater System Performance/Watt

Fabric clock FMAX = 725MHz

GTH max line rate = 16.375 Gb/s

LVDS max rate = 1600Mb/s

FPGA Resources

Chosen DeviceFFsLUTsDSPsBRAM
XCKU060663k221k276038.0Mb
XCKU1151326k663k552075.9Mb

FPGA Hard IP Cores

  • 3x PCI Express Gen3 x8 cores (6 for XCKU115)

On Board Memory

Memory TypeNo. BanksMemory Size (per bank)
SDRAM42GB DDR4-2400

Target FPGA Configuration

  • By PCI Express Bridge on power up
  • By software via PCI Express Bridge
  • Via External JTAG connector

FPGA Configuration Flash

Flash TypeFlash SizeDescription
BPI1GBit2x Bridge, 2x Target, 1x VPD Data Zone
each of 32Mb (bridge) 386Mb (Target)

On-board Clock Specifications

  • Low-jitter 250MHz reference clock, suitable for SerDes applications
  • Low-jitter 200MHz reference clock for IOB delay circuits
  • Custom clock inputs available through the XRM2 interface
  • Two Software-Programmable Clocks

I/O Interfaces

Interface TypeQtyDescription
FRONT I/O (XRM2)
Discrete146LVCMOS/LVDS I/O (programmable to 1.2, 1.5 or 1.8V) to XRM2
High-Speed
Serial Links
8High-Speed Serial Links to XRM2
REAR I/O (Pn6)
High-Speed
Serial Links
10High-Speed Serial Links via Pn6 connector, Standard build has 9 TX/RX data capable links and one external clock input. There is a build option available to use the external clock input as a 10th TX/RX data link.
Discrete I/O38LVCMOS 3.3V GPIO connections via Pn6 connector (VITA 46.9 X8d+X12d+X38s compatible pinout)
REAR I/O (Pn4)
Discrete I/O64Multiple LVCMOS/LVDS GPIO connections via optional PMC Pn4 connector (1.8V levels with 2.5V compatible inputs)
Note: only available with Pn4 Build Option selected

Software

The ADM-XRC-KU1 is supplied with the ADM-XRC-KU1 Support & Development kit (SDK) along with ADB3 Driver for Windows / Linux / VxWorks. (see left)


Ordering Code
ADM-XRC-KU1/z-2(c)(a)(p)(IO)
ParametercodeParameter Description
Kintex Ultrascale devicez

KU060 = XCKU060 FPGA fitted,
KU115 = XCKU115 FPGA fitted

Pn4 Fittedp

blank = not fitted,
/Pn4 = Pn4 connector fitted

Coolingc

blank = air cooled commercial,
/AC1 = air cooled industrial,
/CC1 = conduction cooled industrial

Conformal coatinga

blank = no conformal coating,
A = Acrylic,
P = Polyurethane

IO OptionIO

blank = One differential pair on Pn6 designated as an external clock input,
/10RX = External clock input replaced by 10th data input

Contact sales for other ordering options

Deliverables

  • ADM-XRC-KU1 Board
  • One Year Warranty
  • One Year Technical Support


Sales Questions

For any sales questions regarding the ADM-XRC-KU1, please e-mail us at:

sales@alpha-data.com


Technical Support

For any technical questions regarding Alpha-Data products please e-mail us at:

support@alpha-data.com








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